blob: 055a39773061ac05cb8839d07b4d8d1a0430e701 [file] [log] [blame]
wdenk153d5112002-08-30 11:07:04 +00001/*
2 * (C) Copyright 2001
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include "canbt.h"
26#include <asm/processor.h>
27#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000028
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
wdenk8bde7f72003-06-27 21:31:46 +000030
31/*cmd_boot.c*/
32extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
33
wdenk153d5112002-08-30 11:07:04 +000034
35/* ------------------------------------------------------------------------- */
36
37#if 0
38#define FPGA_DEBUG
39#endif
40
41/* fpga configuration data */
42const unsigned char fpgadata[] = {
43#include "fpgadata.c"
44};
45
46/*
47 * include common fpga code (for esd boards)
48 */
49#include "../common/fpga.c"
50
51
wdenkc837dcb2004-01-20 23:12:12 +000052int board_early_init_f (void)
wdenk153d5112002-08-30 11:07:04 +000053{
wdenk153d5112002-08-30 11:07:04 +000054 unsigned long cntrl0Reg;
55 int index, len, i;
56 int status;
57
58 /*
59 * Setup GPIO pins
60 */
61 cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff;
62 cntrl0Reg |= 0x0070f000;
63 mtdcr (cntrl0, cntrl0Reg);
64
65#ifdef FPGA_DEBUG
66 /* set up serial port with default baudrate */
67 (void) get_clocks ();
68 gd->baudrate = CONFIG_BAUDRATE;
69 serial_init ();
70 console_init_f ();
71#endif
72
73 /*
74 * Boot onboard FPGA
75 */
76 status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
77 if (status != 0) {
78 /* booting FPGA failed */
79#ifndef FPGA_DEBUG
80 /* set up serial port with default baudrate */
81 (void) get_clocks ();
82 gd->baudrate = CONFIG_BAUDRATE;
83 serial_init ();
84 console_init_f ();
85#endif
86 printf ("\nFPGA: Booting failed ");
87 switch (status) {
88 case ERROR_FPGA_PRG_INIT_LOW:
89 printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
90 break;
91 case ERROR_FPGA_PRG_INIT_HIGH:
92 printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
93 break;
94 case ERROR_FPGA_PRG_DONE:
95 printf ("(Timeout: DONE not high after programming FPGA)\n ");
96 break;
97 }
98
99 /* display infos on fpgaimage */
100 index = 15;
101 for (i = 0; i < 4; i++) {
102 len = fpgadata[index];
103 printf ("FPGA: %s\n", &(fpgadata[index + 1]));
104 index += len + 3;
105 }
106 putc ('\n');
107 /* delayed reboot */
108 for (i = 20; i > 0; i--) {
109 printf ("Rebooting in %2d seconds \r", i);
110 for (index = 0; index < 1000; index++)
111 udelay (1000);
112 }
113 putc ('\n');
114 do_reset (NULL, 0, 0, NULL);
115 }
116
117 /*
118 * Setup port pins for normal operation
119 */
stroesec231d002003-05-23 11:32:53 +0000120 out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
121 out32 (GPIO0_TCR, 0x07038100); /* setup for output */
122 out32 (GPIO0_OR, 0x07030100); /* set output pins to high (default) */
wdenk153d5112002-08-30 11:07:04 +0000123
124 /*
125 * IRQ 0-15 405GP internally generated; active high; level sensitive
126 * IRQ 16 405GP internally generated; active low; level sensitive
127 * IRQ 17-24 RESERVED
128 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
129 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
130 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
131 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
132 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
133 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
134 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
135 */
136 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
137 mtdcr (uicer, 0x00000000); /* disable all ints */
138 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
139 mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
140 mtdcr (uictr, 0x10000000); /* set int trigger levels */
141 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
142 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
143
144 return 0;
145}
146
147
148/* ------------------------------------------------------------------------- */
149
150/*
151 * Check Board Identity:
152 */
153
154int checkboard (void)
155{
156 int index;
157 int len;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200158 char str[64];
wdenk153d5112002-08-30 11:07:04 +0000159 int i = getenv_r ("serial#", str, sizeof (str));
160
161 puts ("Board: ");
162
163 if (!i || strncmp (str, "CANBT", 5)) {
164 puts ("### No HW ID - assuming CANBT\n");
165 return (0);
166 }
167
168 puts (str);
169
170 puts ("\nFPGA: ");
171
172 /* display infos on fpgaimage */
173 index = 15;
174 for (i = 0; i < 4; i++) {
175 len = fpgadata[index];
176 printf ("%s ", &(fpgadata[index + 1]));
177 index += len + 3;
178 }
179
180 putc ('\n');
181
182 return 0;
183}
184
185/* ------------------------------------------------------------------------- */
186
187long int initdram (int board_type)
188{
189 return (16 * 1024 * 1024);
190}
191
192/* ------------------------------------------------------------------------- */
193
194int testdram (void)
195{
196 /* TODO: XXX XXX XXX */
197 printf ("test: 16 MB - ok\n");
198
199 return (0);
200}
201
202/* ------------------------------------------------------------------------- */