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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chunhe Lan57072332013-06-14 16:21:48 +08002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Authors: Roy Zang <tie-fei.zang@freescale.com>
6 * Chunhe Lan <Chunhe.Lan@freescale.com>
Chunhe Lan57072332013-06-14 16:21:48 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Chunhe Lan57072332013-06-14 16:21:48 +080012#ifndef CONFIG_SYS_MONITOR_BASE
13#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
14#endif
15
16#ifndef CONFIG_RESET_VECTOR_ADDRESS
17#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
18#endif
19
20/* High Level Configuration Options */
Chunhe Lan57072332013-06-14 16:21:48 +080021
Chunhe Lan57072332013-06-14 16:21:48 +080022#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040023#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
24#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
25#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
Chunhe Lan57072332013-06-14 16:21:48 +080026#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Chunhe Lan57072332013-06-14 16:21:48 +080027#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
Chunhe Lan57072332013-06-14 16:21:48 +080028
29#ifndef __ASSEMBLY__
30extern unsigned long get_clock_freq(void);
31#endif
32
33#define CONFIG_SYS_CLK_FREQ 66666666
34#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
35
36/*
37 * These can be toggled for performance analysis, otherwise use default.
38 */
39#define CONFIG_L2_CACHE /* toggle L2 cache */
40#define CONFIG_BTB /* toggle branch predition */
41#define CONFIG_HWCONFIG
42
43#define CONFIG_ENABLE_36BIT_PHYS
44
45#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
46#define CONFIG_SYS_MEMTEST_END 0x02000000
47
Chunhe Lan57072332013-06-14 16:21:48 +080048/* Implement conversion of addresses in the LBC */
49#define CONFIG_SYS_LBC_LBCR 0x00000000
50#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
51
52/* DDR Setup */
53#define CONFIG_VERY_BIG_RAM
54#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
55#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56
57#define CONFIG_DIMM_SLOTS_PER_CTLR 1
58#define CONFIG_CHIP_SELECTS_PER_CTRL 1
59
60#define CONFIG_DDR_SPD
Chunhe Lan57072332013-06-14 16:21:48 +080061#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
62#define CONFIG_SYS_SPD_BUS_NUM 0
63#define SPD_EEPROM_ADDRESS 0x50
64#define CONFIG_SYS_DDR_RAW_TIMING
65
66/*
67 * Memory map
68 *
69 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
70 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
71 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
72 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
73 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
74 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
75 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
76 *
77 * Localbus non-cacheable
78 *
79 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
80 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
81 */
82
83/*
84 * Local Bus Definitions
85 */
86#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
87#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
88
89#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
90 | BR_PS_16 | BR_V)
91#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
92
Chunhe Lan57072332013-06-14 16:21:48 +080093#define CONFIG_SYS_FLASH_EMPTY_INFO
94#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
95#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
96#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
97#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
98
Chunhe Lan57072332013-06-14 16:21:48 +080099#define CONFIG_SYS_INIT_RAM_LOCK
100#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
101#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
102#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
103 GENERATED_GBL_DATA_SIZE)
104#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530106#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
Chunhe Lan57072332013-06-14 16:21:48 +0800107#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
108
109#define CONFIG_SYS_NAND_BASE 0xffa00000
110#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
111
112#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
113#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan57072332013-06-14 16:21:48 +0800114#define CONFIG_NAND_FSL_ELBC
115#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
116
117/* NAND flash config */
118#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
119 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
120 | BR_PS_8 /* Port Size = 8bit */ \
121 | BR_MS_FCM /* MSEL = FCM */ \
122 | BR_V) /* valid */
123#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
124 | OR_FCM_PGS \
125 | OR_FCM_CSCT \
126 | OR_FCM_CST \
127 | OR_FCM_CHT \
128 | OR_FCM_SCY_1 \
129 | OR_FCM_TRLX \
130 | OR_FCM_EHTR)
131
132#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
133#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
134#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
135#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
136
137/* Serial Port */
Chunhe Lan57072332013-06-14 16:21:48 +0800138#undef CONFIG_SERIAL_SOFTWARE_FIFO
Chunhe Lan57072332013-06-14 16:21:48 +0800139#define CONFIG_SYS_NS16550_SERIAL
140#define CONFIG_SYS_NS16550_REG_SIZE 1
141#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
142
143#define CONFIG_SYS_BAUDRATE_TABLE \
144 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
145
146#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
147#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
148
Chunhe Lan57072332013-06-14 16:21:48 +0800149/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200150#define CONFIG_SYS_I2C
151#define CONFIG_SYS_I2C_FSL
152#define CONFIG_SYS_FSL_I2C_SPEED 400000
153#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
154#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
155#define CONFIG_SYS_FSL_I2C2_SPEED 400000
156#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
157#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Chunhe Lan57072332013-06-14 16:21:48 +0800158
159/*
160 * I2C2 EEPROM
161 */
162#define CONFIG_ID_EEPROM
163#ifdef CONFIG_ID_EEPROM
164#define CONFIG_SYS_I2C_EEPROM_NXID
165#endif
166#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
167#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
168#define CONFIG_SYS_EEPROM_BUS_NUM 0
169
Chunhe Lan57072332013-06-14 16:21:48 +0800170/*
171 * General PCI
172 * Memory space is mapped 1-1, but I/O space must start from 0.
173 */
174
175/* controller 3, Slot 1, tgtid 3, Base address b000 */
176#define CONFIG_SYS_PCIE3_NAME "Slot 3"
177#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
178#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
179#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
180#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
181#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
182#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
183#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
184#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
185
186/* controller 2, direct to uli, tgtid 2, Base address 9000 */
187#define CONFIG_SYS_PCIE2_NAME "Slot 2"
188#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
189#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
190#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
191#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
192#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
193#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
194#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
195#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
196
197/* controller 1, Slot 2, tgtid 1, Base address a000 */
198#define CONFIG_SYS_PCIE1_NAME "Slot 1"
199#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
200#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
201#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
202#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
203#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
204#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
205#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
206#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
207
208#if defined(CONFIG_PCI)
Chunhe Lan57072332013-06-14 16:21:48 +0800209#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
210#endif /* CONFIG_PCI */
211
212/*
213 * Environment
214 */
215#define CONFIG_ENV_OVERWRITE
216
Chunhe Lan57072332013-06-14 16:21:48 +0800217#define CONFIG_LOADS_ECHO /* echo on for serial download */
218#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
219
220/*
Chunhe Lan57072332013-06-14 16:21:48 +0800221 * USB
222 */
223#define CONFIG_HAS_FSL_DR_USB
224#ifdef CONFIG_HAS_FSL_DR_USB
Tom Rini8850c5d2017-05-12 22:33:27 -0400225#ifdef CONFIG_USB_EHCI_HCD
Chunhe Lan57072332013-06-14 16:21:48 +0800226#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
227#define CONFIG_USB_EHCI_FSL
Chunhe Lan57072332013-06-14 16:21:48 +0800228#endif
229#endif
230
231/*
232 * Miscellaneous configurable options
233 */
Chunhe Lan57072332013-06-14 16:21:48 +0800234#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Chunhe Lan57072332013-06-14 16:21:48 +0800235
236/*
237 * For booting Linux, the board info and command line data
238 * have to be in the first 64 MB of memory, since this is
239 * the maximum mapped by the Linux kernel during initialization.
240 */
241#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
242#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
243
244/*
245 * Environment Configuration
246 */
247#define CONFIG_BOOTFILE "uImage"
248#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
249
250/* default location for tftp and bootm */
251#define CONFIG_LOADADDR 1000000
252
Chunhe Lan57072332013-06-14 16:21:48 +0800253/* Qman/Bman */
Chunhe Lan57072332013-06-14 16:21:48 +0800254#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
255#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
256#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500257#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
258#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
259#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
260#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
261#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
262 CONFIG_SYS_QMAN_CENA_SIZE)
263#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
264#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan57072332013-06-14 16:21:48 +0800265#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
266#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
267#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500268#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
269#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
270#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
271#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
272#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
273 CONFIG_SYS_BMAN_CENA_SIZE)
274#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
275#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan57072332013-06-14 16:21:48 +0800276
277/* For FM */
278#define CONFIG_SYS_DPAA_FMAN
Chunhe Lan57072332013-06-14 16:21:48 +0800279
280#ifdef CONFIG_SYS_DPAA_FMAN
Chunhe Lan57072332013-06-14 16:21:48 +0800281#define CONFIG_PHY_ATHEROS
282#endif
283
284/* Default address of microcode for the Linux Fman driver */
285/* QE microcode/firmware address */
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800286#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Chunhe Lan57072332013-06-14 16:21:48 +0800287#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
288#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
289
290#ifdef CONFIG_FMAN_ENET
291#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
292#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
293
294#define CONFIG_SYS_TBIPA_VALUE 8
Chunhe Lan57072332013-06-14 16:21:48 +0800295#define CONFIG_ETHPRIME "FM1@DTSEC1"
296#endif
297
298#define CONFIG_EXTRA_ENV_SETTINGS \
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800299 "netdev=eth0\0" \
300 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
301 "loadaddr=1000000\0" \
302 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
303 "tftpflash=tftpboot $loadaddr $uboot; " \
304 "protect off $ubootaddr +$filesize; " \
305 "erase $ubootaddr +$filesize; " \
306 "cp.b $loadaddr $ubootaddr $filesize; " \
307 "protect on $ubootaddr +$filesize; " \
308 "cmp.b $loadaddr $ubootaddr $filesize\0" \
309 "consoledev=ttyS0\0" \
310 "ramdiskaddr=2000000\0" \
311 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500312 "fdtaddr=1e00000\0" \
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800313 "fdtfile=p1023rdb.dtb\0" \
314 "othbootargs=ramdisk_size=600000\0" \
315 "bdev=sda1\0" \
Chunhe Lan57072332013-06-14 16:21:48 +0800316 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
317
Chunhe Lan5eabbae2014-10-17 16:24:06 +0800318#define CONFIG_HDBOOT \
319 "setenv bootargs root=/dev/$bdev rw " \
320 "console=$consoledev,$baudrate $othbootargs;" \
321 "tftp $loadaddr $bootfile;" \
322 "tftp $fdtaddr $fdtfile;" \
323 "bootm $loadaddr - $fdtaddr"
324
325#define CONFIG_NFSBOOTCOMMAND \
326 "setenv bootargs root=/dev/nfs rw " \
327 "nfsroot=$serverip:$rootpath " \
328 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
329 "console=$consoledev,$baudrate $othbootargs;" \
330 "tftp $loadaddr $bootfile;" \
331 "tftp $fdtaddr $fdtfile;" \
332 "bootm $loadaddr - $fdtaddr"
333
334#define CONFIG_RAMBOOTCOMMAND \
335 "setenv bootargs root=/dev/ram rw " \
336 "console=$consoledev,$baudrate $othbootargs;" \
337 "tftp $ramdiskaddr $ramdiskfile;" \
338 "tftp $loadaddr $bootfile;" \
339 "tftp $fdtaddr $fdtfile;" \
340 "bootm $loadaddr $ramdiskaddr $fdtaddr"
341
342#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
343
Chunhe Lan57072332013-06-14 16:21:48 +0800344#endif /* __CONFIG_H */