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Dave Mitchellb14ca4b2008-11-20 14:00:49 -06001/*
Wolfgang Denk1a459662013-07-08 09:37:19 +02002 * SPDX-License-Identifier: GPL-2.0+
Dave Mitchellb14ca4b2008-11-20 14:00:49 -06003 */
4
5#ifndef _PPC4xx_ISRAM_H_
6#define _PPC4xx_ISRAM_H_
7
8/*
9 * Internal SRAM
10 */
Tirumala Marri1b8fec12010-09-28 14:15:14 -070011#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
12 defined(CONFIG_APM821XX)
Dave Mitchellb14ca4b2008-11-20 14:00:49 -060013#define ISRAM0_DCR_BASE 0x380
14#else
15#define ISRAM0_DCR_BASE 0x020
16#endif
17#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
18#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
19#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
20#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
21#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
22#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
23#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
24#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
25#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
26#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
27#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
28
Tirumala Marri1b8fec12010-09-28 14:15:14 -070029#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
30 defined(CONFIG_APM821XX)
Dave Mitchellb14ca4b2008-11-20 14:00:49 -060031#define ISRAM1_DCR_BASE 0x0B0
32#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
33#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
34#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
35#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
36#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
37#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
38#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
39#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
40#endif /* CONFIG_460EX || CONFIG_460GT */
41
Tirumala Marri1b8fec12010-09-28 14:15:14 -070042#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
43#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
44#elif defined(CONFIG_APM821XX)
45#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
46#endif
47
Dave Mitchellb14ca4b2008-11-20 14:00:49 -060048/*
49 * L2 Cache
50 */
51#if defined (CONFIG_440GX) || \
52 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
53 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Tirumala Marri1b8fec12010-09-28 14:15:14 -070054 defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
Dave Mitchellb14ca4b2008-11-20 14:00:49 -060055#define L2_CACHE_BASE 0x030
56#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
57#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
58#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
59#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
60#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
61#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
62#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
63#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
64#endif /* CONFIG_440GX */
65
66#endif /* _PPC4xx_ISRAM_H_ */