Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Exceet Electronics GmbH |
| 4 | * Copyright (C) 2018 Bootlin |
| 5 | * |
| 6 | * Author: |
| 7 | * Peter Pan <peterpandong@micron.com> |
| 8 | * Boris Brezillon <boris.brezillon@bootlin.com> |
| 9 | */ |
| 10 | |
| 11 | #ifndef __UBOOT_SPI_MEM_H |
| 12 | #define __UBOOT_SPI_MEM_H |
| 13 | |
Simon Glass | 340fd10 | 2020-07-19 10:15:34 -0600 | [diff] [blame] | 14 | struct udevice; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 15 | |
| 16 | #define SPI_MEM_OP_CMD(__opcode, __buswidth) \ |
| 17 | { \ |
| 18 | .buswidth = __buswidth, \ |
| 19 | .opcode = __opcode, \ |
| 20 | } |
| 21 | |
| 22 | #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ |
| 23 | { \ |
| 24 | .nbytes = __nbytes, \ |
| 25 | .val = __val, \ |
| 26 | .buswidth = __buswidth, \ |
| 27 | } |
| 28 | |
| 29 | #define SPI_MEM_OP_NO_ADDR { } |
| 30 | |
| 31 | #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ |
| 32 | { \ |
| 33 | .nbytes = __nbytes, \ |
| 34 | .buswidth = __buswidth, \ |
| 35 | } |
| 36 | |
| 37 | #define SPI_MEM_OP_NO_DUMMY { } |
| 38 | |
| 39 | #define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ |
| 40 | { \ |
| 41 | .dir = SPI_MEM_DATA_IN, \ |
| 42 | .nbytes = __nbytes, \ |
| 43 | .buf.in = __buf, \ |
| 44 | .buswidth = __buswidth, \ |
| 45 | } |
| 46 | |
| 47 | #define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ |
| 48 | { \ |
| 49 | .dir = SPI_MEM_DATA_OUT, \ |
| 50 | .nbytes = __nbytes, \ |
| 51 | .buf.out = __buf, \ |
| 52 | .buswidth = __buswidth, \ |
| 53 | } |
| 54 | |
| 55 | #define SPI_MEM_OP_NO_DATA { } |
| 56 | |
| 57 | /** |
| 58 | * enum spi_mem_data_dir - describes the direction of a SPI memory data |
| 59 | * transfer from the controller perspective |
Tudor Ambarus | 790c169 | 2020-03-20 09:35:31 +0000 | [diff] [blame] | 60 | * @SPI_MEM_NO_DATA: no data transferred |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 61 | * @SPI_MEM_DATA_IN: data coming from the SPI memory |
| 62 | * @SPI_MEM_DATA_OUT: data sent the SPI memory |
| 63 | */ |
| 64 | enum spi_mem_data_dir { |
Tudor Ambarus | 790c169 | 2020-03-20 09:35:31 +0000 | [diff] [blame] | 65 | SPI_MEM_NO_DATA, |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 66 | SPI_MEM_DATA_IN, |
| 67 | SPI_MEM_DATA_OUT, |
| 68 | }; |
| 69 | |
| 70 | /** |
| 71 | * struct spi_mem_op - describes a SPI memory operation |
| 72 | * @cmd.buswidth: number of IO lines used to transmit the command |
| 73 | * @cmd.opcode: operation opcode |
| 74 | * @addr.nbytes: number of address bytes to send. Can be zero if the operation |
| 75 | * does not need to send an address |
| 76 | * @addr.buswidth: number of IO lines used to transmit the address cycles |
| 77 | * @addr.val: address value. This value is always sent MSB first on the bus. |
| 78 | * Note that only @addr.nbytes are taken into account in this |
| 79 | * address value, so users should make sure the value fits in the |
| 80 | * assigned number of bytes. |
| 81 | * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can |
| 82 | * be zero if the operation does not require dummy bytes |
| 83 | * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes |
| 84 | * @data.buswidth: number of IO lanes used to send/receive the data |
| 85 | * @data.dir: direction of the transfer |
| 86 | * @data.buf.in: input buffer |
| 87 | * @data.buf.out: output buffer |
| 88 | */ |
| 89 | struct spi_mem_op { |
| 90 | struct { |
| 91 | u8 buswidth; |
| 92 | u8 opcode; |
| 93 | } cmd; |
| 94 | |
| 95 | struct { |
| 96 | u8 nbytes; |
| 97 | u8 buswidth; |
| 98 | u64 val; |
| 99 | } addr; |
| 100 | |
| 101 | struct { |
| 102 | u8 nbytes; |
| 103 | u8 buswidth; |
| 104 | } dummy; |
| 105 | |
| 106 | struct { |
| 107 | u8 buswidth; |
| 108 | enum spi_mem_data_dir dir; |
| 109 | unsigned int nbytes; |
| 110 | /* buf.{in,out} must be DMA-able. */ |
| 111 | union { |
| 112 | void *in; |
| 113 | const void *out; |
| 114 | } buf; |
| 115 | } data; |
| 116 | }; |
| 117 | |
| 118 | #define SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ |
| 119 | { \ |
| 120 | .cmd = __cmd, \ |
| 121 | .addr = __addr, \ |
| 122 | .dummy = __dummy, \ |
| 123 | .data = __data, \ |
| 124 | } |
| 125 | |
| 126 | #ifndef __UBOOT__ |
| 127 | /** |
| 128 | * struct spi_mem - describes a SPI memory device |
| 129 | * @spi: the underlying SPI device |
| 130 | * @drvpriv: spi_mem_driver private data |
| 131 | * |
| 132 | * Extra information that describe the SPI memory device and may be needed by |
| 133 | * the controller to properly handle this device should be placed here. |
| 134 | * |
| 135 | * One example would be the device size since some controller expose their SPI |
| 136 | * mem devices through a io-mapped region. |
| 137 | */ |
| 138 | struct spi_mem { |
| 139 | struct udevice *dev; |
| 140 | void *drvpriv; |
| 141 | }; |
| 142 | |
| 143 | /** |
| 144 | * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem |
| 145 | * device |
| 146 | * @mem: memory device |
| 147 | * @data: data to attach to the memory device |
| 148 | */ |
| 149 | static inline void spi_mem_set_drvdata(struct spi_mem *mem, void *data) |
| 150 | { |
| 151 | mem->drvpriv = data; |
| 152 | } |
| 153 | |
| 154 | /** |
| 155 | * struct spi_mem_get_drvdata() - get driver private data attached to a SPI mem |
| 156 | * device |
| 157 | * @mem: memory device |
| 158 | * |
| 159 | * Return: the data attached to the mem device. |
| 160 | */ |
| 161 | static inline void *spi_mem_get_drvdata(struct spi_mem *mem) |
| 162 | { |
| 163 | return mem->drvpriv; |
| 164 | } |
| 165 | #endif /* __UBOOT__ */ |
| 166 | |
| 167 | /** |
| 168 | * struct spi_controller_mem_ops - SPI memory operations |
| 169 | * @adjust_op_size: shrink the data xfer of an operation to match controller's |
| 170 | * limitations (can be alignment of max RX/TX size |
| 171 | * limitations) |
| 172 | * @supports_op: check if an operation is supported by the controller |
| 173 | * @exec_op: execute a SPI memory operation |
| 174 | * |
| 175 | * This interface should be implemented by SPI controllers providing an |
| 176 | * high-level interface to execute SPI memory operation, which is usually the |
| 177 | * case for QSPI controllers. |
| 178 | */ |
| 179 | struct spi_controller_mem_ops { |
| 180 | int (*adjust_op_size)(struct spi_slave *slave, struct spi_mem_op *op); |
| 181 | bool (*supports_op)(struct spi_slave *slave, |
| 182 | const struct spi_mem_op *op); |
| 183 | int (*exec_op)(struct spi_slave *slave, |
| 184 | const struct spi_mem_op *op); |
| 185 | }; |
| 186 | |
| 187 | #ifndef __UBOOT__ |
| 188 | /** |
| 189 | * struct spi_mem_driver - SPI memory driver |
| 190 | * @spidrv: inherit from a SPI driver |
| 191 | * @probe: probe a SPI memory. Usually where detection/initialization takes |
| 192 | * place |
| 193 | * @remove: remove a SPI memory |
| 194 | * @shutdown: take appropriate action when the system is shutdown |
| 195 | * |
| 196 | * This is just a thin wrapper around a spi_driver. The core takes care of |
| 197 | * allocating the spi_mem object and forwarding the probe/remove/shutdown |
| 198 | * request to the spi_mem_driver. The reason we use this wrapper is because |
| 199 | * we might have to stuff more information into the spi_mem struct to let |
| 200 | * SPI controllers know more about the SPI memory they interact with, and |
| 201 | * having this intermediate layer allows us to do that without adding more |
| 202 | * useless fields to the spi_device object. |
| 203 | */ |
| 204 | struct spi_mem_driver { |
| 205 | struct spi_driver spidrv; |
| 206 | int (*probe)(struct spi_mem *mem); |
| 207 | int (*remove)(struct spi_mem *mem); |
| 208 | void (*shutdown)(struct spi_mem *mem); |
| 209 | }; |
| 210 | |
| 211 | #if IS_ENABLED(CONFIG_SPI_MEM) |
| 212 | int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, |
| 213 | const struct spi_mem_op *op, |
| 214 | struct sg_table *sg); |
| 215 | |
| 216 | void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, |
| 217 | const struct spi_mem_op *op, |
| 218 | struct sg_table *sg); |
| 219 | #else |
| 220 | static inline int |
| 221 | spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, |
| 222 | const struct spi_mem_op *op, |
| 223 | struct sg_table *sg) |
| 224 | { |
| 225 | return -ENOTSUPP; |
| 226 | } |
| 227 | |
| 228 | static inline void |
| 229 | spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, |
| 230 | const struct spi_mem_op *op, |
| 231 | struct sg_table *sg) |
| 232 | { |
| 233 | } |
| 234 | #endif /* CONFIG_SPI_MEM */ |
| 235 | #endif /* __UBOOT__ */ |
| 236 | |
| 237 | int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op); |
| 238 | |
| 239 | bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); |
| 240 | |
| 241 | int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op); |
| 242 | |
Mathew McBride | af6266c | 2021-01-25 03:55:20 +0000 | [diff] [blame] | 243 | bool spi_mem_default_supports_op(struct spi_slave *mem, |
| 244 | const struct spi_mem_op *op); |
| 245 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 246 | #ifndef __UBOOT__ |
| 247 | int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv, |
| 248 | struct module *owner); |
| 249 | |
| 250 | void spi_mem_driver_unregister(struct spi_mem_driver *drv); |
| 251 | |
| 252 | #define spi_mem_driver_register(__drv) \ |
| 253 | spi_mem_driver_register_with_owner(__drv, THIS_MODULE) |
| 254 | |
| 255 | #define module_spi_mem_driver(__drv) \ |
| 256 | module_driver(__drv, spi_mem_driver_register, \ |
| 257 | spi_mem_driver_unregister) |
| 258 | #endif |
| 259 | |
| 260 | #endif /* __LINUX_SPI_MEM_H */ |