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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese21b29fc2016-05-25 08:13:45 +02002/*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
Stefan Roese21b29fc2016-05-25 08:13:45 +02004 */
5
6#include <common.h>
7#include <dm.h>
8#include <fdtdec.h>
Simon Glass67c4e9f2019-11-14 12:57:45 -07009#include <init.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090010#include <linux/libfdt.h>
Baruch Siach2b4d9642018-11-11 12:31:04 +020011#include <linux/sizes.h>
Konstantin Porotchkinf4f194e2017-04-05 17:42:33 +030012#include <pci.h>
Stefan Roese21b29fc2016-05-25 08:13:45 +020013#include <asm/io.h>
14#include <asm/system.h>
15#include <asm/arch/cpu.h>
16#include <asm/arch/soc.h>
17#include <asm/armv8/mmu.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21/*
Stefan Roese059f75d2016-11-11 08:18:44 +010022 * Not all memory is mapped in the MMU. So we need to restrict the
23 * memory size so that U-Boot does not try to access it. Also, the
24 * internal registers are located at 0xf000.0000 - 0xffff.ffff.
25 * Currently only 2GiB are mapped for system memory. This is what
26 * we pass to the U-Boot subsystem here.
27 */
28#define USABLE_RAM_SIZE 0x80000000
29
30ulong board_get_usable_ram_top(ulong total_size)
31{
32 if (gd->ram_size > USABLE_RAM_SIZE)
33 return USABLE_RAM_SIZE;
34
35 return gd->ram_size;
36}
37
38/*
Stefan Roese21b29fc2016-05-25 08:13:45 +020039 * On ARMv8, MBus is not configured in U-Boot. To enable compilation
40 * of the already implemented drivers, lets add a dummy version of
41 * this function so that linking does not fail.
42 */
43const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
44{
45 return NULL;
46}
47
Marek Behún3b281ac2018-12-17 16:10:09 +010048__weak int dram_init_banksize(void)
Stefan Roese21b29fc2016-05-25 08:13:45 +020049{
Baruch Siach2b4d9642018-11-11 12:31:04 +020050 if (CONFIG_IS_ENABLED(ARMADA_8K))
Marek Behúnf075b422020-04-08 19:25:18 +020051 return a8k_dram_init_banksize();
Baruch Siach2b4d9642018-11-11 12:31:04 +020052 else
Marek Behúnf075b422020-04-08 19:25:18 +020053 return fdtdec_setup_memory_banksize();
Stefan Roese21b29fc2016-05-25 08:13:45 +020054}
55
Marek Behún3b281ac2018-12-17 16:10:09 +010056__weak int dram_init(void)
Stefan Roese21b29fc2016-05-25 08:13:45 +020057{
Baruch Siach2b4d9642018-11-11 12:31:04 +020058 if (CONFIG_IS_ENABLED(ARMADA_8K)) {
59 gd->ram_size = a8k_dram_scan_ap_sz();
60 if (gd->ram_size != 0)
61 return 0;
62 }
63
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +053064 if (fdtdec_setup_mem_size_base() != 0)
Stefan Roese780f80c2017-05-08 08:31:30 +020065 return -EINVAL;
Simon Glass76b00ac2017-03-31 08:40:32 -060066
67 return 0;
Stefan Roese21b29fc2016-05-25 08:13:45 +020068}
69
70int arch_cpu_init(void)
71{
72 /* Nothing to do (yet) */
73 return 0;
74}
75
76int arch_early_init_r(void)
77{
78 struct udevice *dev;
79 int ret;
Stefan Roesed7dd3582016-10-25 18:12:40 +020080 int i;
Stefan Roese21b29fc2016-05-25 08:13:45 +020081
Stefan Roesed7dd3582016-10-25 18:12:40 +020082 /*
83 * Loop over all MISC uclass drivers to call the comphy code
84 * and init all CP110 devices enabled in the DT
85 */
86 i = 0;
87 while (1) {
88 /* Call the comphy code via the MISC uclass driver */
89 ret = uclass_get_device(UCLASS_MISC, i++, &dev);
90
91 /* We're done, once no further CP110 device is found */
92 if (ret)
93 break;
Stefan Roese21b29fc2016-05-25 08:13:45 +020094 }
95
96 /* Cause the SATA device to do its early init */
97 uclass_first_device(UCLASS_AHCI, &dev);
98
Konstantin Porotchkinf4f194e2017-04-05 17:42:33 +030099#ifdef CONFIG_DM_PCI
100 /* Trigger PCIe devices detection */
101 pci_init();
102#endif
103
Stefan Roese21b29fc2016-05-25 08:13:45 +0200104 return 0;
105}