blob: 77e115877057d30c4d357143fa7889cf6e5f3896 [file] [log] [blame]
Heiko Schocheradf22b62008-08-19 10:08:49 +02001/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_8260 1
33#define CONFIG_MPC8260 1
34#define CONFIG_MUAS3001 1
35
36#define CONFIG_CPM2 1 /* Has a CPM2 */
37
38/* Do boardspecific init */
39#define CONFIG_BOARD_EARLY_INIT_R 1
40
41/*
42 * Select serial console configuration
43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 */
48#define CONFIG_CONS_ON_SMC /* Console is on SMC */
49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50#undef CONFIG_CONS_NONE /* It's not on external UART */
51#if defined(CONFIG_MUAS_DEV_BOARD)
52#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
53#else
54#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
55#endif
56
57/*
58 * Select ethernet configuration
59 *
60 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
61 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
62 * SCC, 1-3 for FCC)
63 *
64 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
65 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
66 * must be unset.
67 */
68#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
69#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
70#undef CONFIG_ETHER_NONE /* No external Ethernet */
71
72#define CONFIG_ETHER_INDEX 1
73#define CONFIG_ETHER_ON_FCC1
74#define FCC_ENET
75
76/*
77 * - Rx-CLK is CLK11
78 * - Tx-CLK is CLK12
79 */
80# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
81# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
82/*
83 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
84 */
85# define CFG_CPMFCR_RAMTYPE (0)
86/* know on local Bus */
87/* define CFG_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
88/*
89 * - Enable Full Duplex in FSMR
90 */
91# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
92
93#define CONFIG_MII /* MII PHY management */
94#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
95# define CFG_PHY_ADDR 1
96/*
97 * GPIO pins used for bit-banged MII communications
98 */
99#define MDIO_PORT 0 /* Port A */
100
101#define CFG_MDIO_PIN 0x00200000 /* PA10 */
102#define CFG_MDC_PIN 0x00400000 /* PA9 */
103
104#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
105#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
106#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
107
108#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
109 else iop->pdat &= ~CFG_MDIO_PIN
110
111#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
112 else iop->pdat &= ~CFG_MDC_PIN
113
114#define MIIDELAY udelay(1)
115
116#ifndef CONFIG_8260_CLKIN
117#define CONFIG_8260_CLKIN 66000000 /* in Hz */
118#endif
119
120#define CONFIG_BAUDRATE 115200
121
122/*
123 * Command line configuration.
124 */
125#include <config_cmd_default.h>
126
127#define CONFIG_CMD_ECHO
128#define CONFIG_CMD_IMMAP
129#define CONFIG_CMD_MII
130#define CONFIG_CMD_PING
131#define CONFIG_CMD_I2C
132
133/*
134 * Default environment settings
135 */
136#define CONFIG_EXTRA_ENV_SETTINGS \
137 "netdev=eth0\0" \
138 "u-boot_addr_r=100000\0" \
139 "kernel_addr_r=200000\0" \
140 "fdt_addr_r=400000\0" \
141 "rootpath=/opt/eldk/ppc_6xx\0" \
142 "u-boot=muas3001/u-boot.bin\0" \
143 "bootfile=muas3001/uImage\0" \
144 "fdt_file=muas3001/muas3001.dtb\0" \
145 "ramdisk_file=uRamdisk\0" \
146 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
147 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
148 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
149 "prot on ff000000 ff03ffff\0" \
150 "ramargs=setenv bootargs root=/dev/ram rw\0" \
151 "nfsargs=setenv bootargs root=/dev/nfs rw " \
152 "nfsroot=${serverip}:${rootpath}\0" \
153 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
154 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
155 "addip=setenv bootargs ${bootargs} " \
156 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
157 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
158 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
159 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
160 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
161 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
162 "tftp ${fdt_addr_r} ${fdt_file}; " \
163 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
164 "run ramargs addip; " \
165 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
166 "ramdisk_addr=ff210000\0" \
167 "kernel_addr=ff050000\0" \
168 "fdt_addr=ff200000\0" \
169 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
170 " ${ramdisk_addr} ${fdt_addr}\0" \
171 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
172 " ${ramdisk_file};" \
173 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
174 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
175 " ${bootfile};" \
176 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
177 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
178 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
179 ""
180
181#define CONFIG_BOOTCOMMAND "run net_nfs"
182#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
183
184#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
185
186/*
187 * Miscellaneous configurable options
188 */
189#define CFG_HUSH_PARSER
190#define CFG_PROMPT_HUSH_PS2 "> "
191#define CFG_LONGHELP /* undef to save memory */
192#define CFG_PROMPT "=> " /* Monitor Command Prompt */
193#if defined(CONFIG_CMD_KGDB)
194#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
195#else
196#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
197#endif
198#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
199#define CFG_MAXARGS 16 /* max number of command args */
200#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
201
202#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
203#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
204
205#define CFG_LOAD_ADDR 0x100000 /* default load address */
206
207#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
208
209#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
210
211#define CFG_SDRAM_BASE 0x00000000
212#define CFG_FLASH_BASE 0xFF000000
213#define CFG_FLASH_SIZE 32
214#define CFG_FLASH_CFI
215#define CONFIG_FLASH_CFI_DRIVER
216#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
217#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
218
219#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
220
221#define CFG_MONITOR_BASE TEXT_BASE
222#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
223#define CFG_RAMBOOT
224#endif
225
226#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
227
228#define CFG_ENV_IS_IN_FLASH
229
230#ifdef CFG_ENV_IS_IN_FLASH
231#define CFG_ENV_SECT_SIZE 0x10000
232#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
233#endif /* CFG_ENV_IS_IN_FLASH */
234
235/*
236 * I2C Bus
237 */
238#define CONFIG_HARD_I2C 1 /* To enable I2C support */
239#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
240#define CFG_I2C_SLAVE 0x7F
241
242#define CFG_IMMR 0xF0000000
243#define CFG_DEFAULT_IMMR 0x0F010000
244
245#define CFG_INIT_RAM_ADDR CFG_IMMR
246#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
247#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
248#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
249#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
250
251/* Hard reset configuration word */
252#define CFG_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
253
254/* No slaves */
255#define CFG_HRCW_SLAVE1 0
256#define CFG_HRCW_SLAVE2 0
257#define CFG_HRCW_SLAVE3 0
258#define CFG_HRCW_SLAVE4 0
259#define CFG_HRCW_SLAVE5 0
260#define CFG_HRCW_SLAVE6 0
261#define CFG_HRCW_SLAVE7 0
262
263#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
264#define BOOTFLAG_WARM 0x02 /* Software reboot */
265
266#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
267#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
268
269#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
270#if defined(CONFIG_CMD_KGDB)
271# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
272#endif
273
274#define CFG_HID0_INIT 0
275#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
276
277#define CFG_HID2 0
278
279#define CFG_SIUMCR 0x00200000
280#define CFG_SYPCR 0xFFFFFFC3
281#define CFG_BCR 0x004c0000
282#define CFG_SCCR 0x0
283
284/*-----------------------------------------------------------------------
285 * RMR - Reset Mode Register 5-5
286 *-----------------------------------------------------------------------
287 * turn on Checkstop Reset Enable
288 */
289#define CFG_RMR 0
290
291/*-----------------------------------------------------------------------
292 * TMCNTSC - Time Counter Status and Control 4-40
293 *-----------------------------------------------------------------------
294 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
295 * and enable Time Counter
296 */
297#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
298
299/*-----------------------------------------------------------------------
300 * PISCR - Periodic Interrupt Status and Control 4-42
301 *-----------------------------------------------------------------------
302 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
303 * Periodic timer
304 */
305#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
306
307/*-----------------------------------------------------------------------
308 * RCCR - RISC Controller Configuration 13-7
309 *-----------------------------------------------------------------------
310 */
311#define CFG_RCCR 0
312
313/*
314 * Init Memory Controller:
315 *
316 * Bank Bus Machine PortSz Device
317 * ---- --- ------- ------ ------
318 * 0 60x GPCM 32 bit FLASH
319 * 1 60x SDRAM 64 bit SDRAM
320 * 4 60x GPCM 16 bit I/O Ctrl
321 *
322 */
323/* Bank 0 - FLASH
324 */
325#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
326 BRx_PS_32 |\
327 BRx_MS_GPCM_P |\
328 BRx_V)
329
330#define CFG_OR0_PRELIM (0xff000020)
331
332/* Bank 1 - 60x bus SDRAM
333 */
334#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
335#define CFG_GLOBAL_SDRAM_LIMIT (128 << 20) /* less than 128 MB */
336
337#define CFG_MPTPR 0x2800
338
339/*-----------------------------------------------------------------------------
340 * Address for Mode Register Set (MRS) command
341 *-----------------------------------------------------------------------------
342 */
343#define CFG_MRS_OFFS 0x00000110
344#define CFG_PSRT 0x13
345
346#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
347 BRx_PS_64 |\
348 BRx_MS_SDRAM_P |\
349 BRx_V)
350
351#define CFG_OR1_PRELIM CFG_OR1
352
353/* SDRAM initialization values
354*/
355#define CFG_OR1 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
356 ORxS_BPD_4 |\
357 ORxS_ROWST_PBI1_A7 |\
358 ORxS_NUMR_12)
359
360#define CFG_PSDMR 0x004b36a3
361
362/* IO on CS4 initialization values
363*/
364#define CFG_IO_BASE 0xc0000000
365#define CFG_IO_SIZE 1
366
367#define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\
368 BRx_PS_32 | BRx_MS_GPCM_L | BRx_V)
369
370#define CFG_OR4_PRELIM (0xfff80020)
371
372#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
373
374/* pass open firmware flat tree */
375#define CONFIG_OF_LIBFDT 1
376#define CONFIG_OF_BOARD_SETUP 1
377
378#define OF_CPU "PowerPC,8270@0"
379#define OF_SOC "soc@f0000000"
380#define OF_TBCLK (bd->bi_busfreq / 4)
381#if defined(CONFIG_MUAS_DEV_BOARD)
382#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
383#else
384#define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
385#endif
386
387#endif /* __CONFIG_H */