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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a62b7f0c24803528e82d88072050deaa0fc8775b / . / include / configs / hsdk-4xd.h
blob: 7785bab7147b6dd988a05574fe450f8635425201 [file] [log] [blame]
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
5 */
6
7#ifndef _CONFIG_HSDK_H_
8#define _CONFIG_HSDK_H_
9
10#include <linux/sizes.h>
11
12/*
13 * CPU configuration
14 */
15#define NR_CPUS 4
16#define ARC_PERIPHERAL_BASE 0xF0000000
17#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
18#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
19
20/*
21 * Memory configuration
22 */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]23
24#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26#define CONFIG_SYS_SDRAM_SIZE SZ_1G
27
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]28#define CONFIG_SYS_BOOTM_LEN SZ_128M
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]29
30/*
31 * UART configuration
32 */
33#define CONFIG_SYS_NS16550_SERIAL
34#define CONFIG_SYS_NS16550_CLK 33330000
35#define CONFIG_SYS_NS16550_MEM32
36
37/*
38 * Ethernet PHY configuration
39 */
40
41/*
42 * USB 1.1 configuration
43 */
44#define CONFIG_USB_OHCI_NEW
45#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
46
47/*
48 * Environment settings
49 */
50#define CONFIG_EXTRA_ENV_SETTINGS \
51 "upgrade=if mmc rescan && " \
52 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
53 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
54 "\"Fail to upgrade.\n" \
55 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
56 "; fi\0" \
57 "core_mask=0xF\0" \
58 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
59setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
60setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
61setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
62 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
63setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
64setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
65setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
66 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
67setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
68setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
69setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
70 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
71setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
72setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
73setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
74 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
75setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
76setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
77setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
78 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
79 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
80setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
81setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
82setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
83setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
84 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
85 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
86setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
87setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
88setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
89setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
90setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
91 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
92 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
93setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
94setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
95setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
96setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
97setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
98setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
99
100/*
101 * Environment configuration
102 */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]103
104/* Cli configuration */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]105
106/*
107 * Callback configuration
108 */
Eugeniy Paltsev3ad73b72020-04-22 02:59:31 +0300[diff] [blame]109
110#endif /* _CONFIG_HSDK_H_ */