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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Matt Waddelb80e41a2010-10-07 15:48:45 -06002/*
Ryan Harkincd4f46e2013-04-09 02:20:31 +00003 * (C) Copyright 2011 ARM Limited
Matt Waddelb80e41a2010-10-07 15:48:45 -06004 * (C) Copyright 2010 Linaro
5 * Matt Waddel, <matt.waddel@linaro.org>
6 *
7 * Configuration for Versatile Express. Parts were derived from other ARM
8 * configurations.
Matt Waddelb80e41a2010-10-07 15:48:45 -06009 */
10
Ryan Harkincd4f46e2013-04-09 02:20:31 +000011#ifndef __VEXPRESS_COMMON_H
12#define __VEXPRESS_COMMON_H
13
14/*
15 * Definitions copied from linux kernel:
16 * arch/arm/mach-vexpress/include/mach/motherboard.h
17 */
Kristian Amlie8a0f5f62021-09-10 08:19:19 +020018#ifdef VEXPRESS_ORIGINAL_MEMORY_MAP
Ryan Harkincd4f46e2013-04-09 02:20:31 +000019/* CS register bases for the original memory map. */
20#define V2M_PA_CS0 0x40000000
21#define V2M_PA_CS1 0x44000000
22#define V2M_PA_CS2 0x48000000
23#define V2M_PA_CS3 0x4c000000
24#define V2M_PA_CS7 0x10000000
25
26#define V2M_PERIPH_OFFSET(x) (x << 12)
27#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
28#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
29#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
30
31#define V2M_BASE 0x60000000
Ryan Harkincd4f46e2013-04-09 02:20:31 +000032#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
33/* CS register bases for the extended memory map. */
34#define V2M_PA_CS0 0x08000000
35#define V2M_PA_CS1 0x0c000000
36#define V2M_PA_CS2 0x14000000
37#define V2M_PA_CS3 0x18000000
38#define V2M_PA_CS7 0x1c000000
39
40#define V2M_PERIPH_OFFSET(x) (x << 16)
41#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
42#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
43#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
44
45#define V2M_BASE 0x80000000
Ryan Harkincd4f46e2013-04-09 02:20:31 +000046#endif
47
48/*
49 * Physical addresses, offset from V2M_PA_CS0-3
50 */
51#define V2M_NOR0 (V2M_PA_CS0)
52#define V2M_NOR1 (V2M_PA_CS1)
53#define V2M_SRAM (V2M_PA_CS2)
54#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
Ryan Harkincd4f46e2013-04-09 02:20:31 +000055#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
56
57/* Common peripherals relative to CS7. */
58#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
Ryan Harkincd4f46e2013-04-09 02:20:31 +000059#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
60#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
61
62#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
63#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
64#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
65#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
66
67#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
68
69#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
70#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
71
72#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
73#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
74
75#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
76
77#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
78#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
79
80/* System register offsets. */
81#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
82#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
83#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
84
85/*
86 * Configuration
87 */
88#define SYS_CFG_START (1 << 31)
89#define SYS_CFG_WRITE (1 << 30)
90#define SYS_CFG_OSC (1 << 20)
91#define SYS_CFG_VOLT (2 << 20)
92#define SYS_CFG_AMP (3 << 20)
93#define SYS_CFG_TEMP (4 << 20)
94#define SYS_CFG_RESET (5 << 20)
95#define SYS_CFG_SCC (6 << 20)
96#define SYS_CFG_MUXFPGA (7 << 20)
97#define SYS_CFG_SHUTDOWN (8 << 20)
98#define SYS_CFG_REBOOT (9 << 20)
99#define SYS_CFG_DVIMODE (11 << 20)
100#define SYS_CFG_POWER (12 << 20)
101#define SYS_CFG_SITE_MB (0 << 16)
102#define SYS_CFG_SITE_DB1 (1 << 16)
103#define SYS_CFG_SITE_DB2 (2 << 16)
104#define SYS_CFG_STACK(n) ((n) << 12)
105
106#define SYS_CFG_ERR (1 << 1)
107#define SYS_CFG_COMPLETE (1 << 0)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600108
109/* Board info register */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000110#define SYS_ID V2M_SYSREGS
Matt Waddelb80e41a2010-10-07 15:48:45 -0600111
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000112#define SCTL_BASE V2M_SYSCTL
Matt Waddelb80e41a2010-10-07 15:48:45 -0600113#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
114
Rob Herringb3a7f222013-10-04 10:22:45 -0500115#define CONFIG_SYS_TIMER_RATE 1000000
Ian Campbellcb7ee1b2013-11-17 15:17:42 +0000116#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
Rob Herringb3a7f222013-10-04 10:22:45 -0500117#define CONFIG_SYS_TIMER_COUNTS_DOWN
118
Matt Waddelb80e41a2010-10-07 15:48:45 -0600119/* PL011 Serial Configuration */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600120#define CONFIG_PL011_CLOCK 24000000
121#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
122 (void *)CONFIG_SYS_SERIAL1}
Matt Waddelb80e41a2010-10-07 15:48:45 -0600123
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000124#define CONFIG_SYS_SERIAL0 V2M_UART0
125#define CONFIG_SYS_SERIAL1 V2M_UART1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600126
Matt Waddelf0c64522011-04-16 11:54:08 +0000127#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
Matt Waddelb80e41a2010-10-07 15:48:45 -0600128
Matt Waddelb80e41a2010-10-07 15:48:45 -0600129/* Miscellaneous configurable options */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000130#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600131
Matt Waddelb80e41a2010-10-07 15:48:45 -0600132/* Physical Memory Map */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000133#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
134#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
135 ((unsigned int)0x20000000))
Matt Waddelb80e41a2010-10-07 15:48:45 -0600136#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
137#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
138
139/* additions for new relocation code */
140#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk553f0982010-10-26 13:32:32 +0200141#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500142
Matt Waddelb80e41a2010-10-07 15:48:45 -0600143/* Basic environment settings */
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500144#define BOOT_TARGET_DEVICES(func) \
145 func(MMC, mmc, 1) \
146 func(MMC, mmc, 0) \
147 func(PXE, pxe, na) \
148 func(DHCP, dhcp, na)
149#include <config_distro_bootcmd.h>
150
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000151#define CONFIG_EXTRA_ENV_SETTINGS \
Kristian Amlie15e30102021-09-07 08:37:51 +0200152 "kernel_addr_r=0x60100000\0" \
153 "fdt_addr_r=0x60000000\0" \
154 "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500155 BOOTENV \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600156 "console=ttyAMA0,38400n8\0" \
157 "dram=1024M\0" \
158 "root=/dev/sda1 rw\0" \
159 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
160 "24M@0x2000000(initrd)\0" \
161 "flashargs=setenv bootargs root=${root} console=${console} " \
162 "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
163 "devtmpfs.mount=0 vmalloc=256M\0" \
164 "bootflash=run flashargs; " \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000165 "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
Kristian Amlied4babee2020-02-25 18:22:16 +0100166 "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \
167 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
Matt Waddelb80e41a2010-10-07 15:48:45 -0600168
169/* FLASH and environment organization */
170#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600171#define CONFIG_SYS_FLASH_SIZE 0x04000000
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000172#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
173#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600174
175/* Timeout values in ticks */
176#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
177#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
178
179/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
180#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
181#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
182
183/* Room required on the stack for the environment data */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600184
Matt Waddelb80e41a2010-10-07 15:48:45 -0600185/*
186 * Amount of flash used for environment:
187 * We don't know which end has the small erase blocks so we use the penultimate
188 * sector location for the environment
189 */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600190
191/* Store environment at top of flash */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600192#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
193#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
194 CONFIG_SYS_FLASH_BASE1 }
195
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000196#endif /* VEXPRESS_COMMON_H */