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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a6bcd977f94c45d3b3f5615d4aeeb6f3ff3b45fc / . / arch / arm / dts / imxrt1170.dtsi
blob: 2de775f043ffc7ee57b623d623e12e85f6ee38f1 [file] [log] [blame]
Jesse Taube505efde2022-07-26 01:43:45 -0400[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2022
4 * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
5 * Giulio Benetti <giulio.benetti@benettiengineering.com>
6 */
7
8#include "armv7-m.dtsi"
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/imxrt1170-clock.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/memory/imxrt-sdram.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 gpio5 = &gpio6;
25 gpio6 = &gpio7;
26 gpio7 = &gpio8;
27 gpio8 = &gpio9;
28 gpio9 = &gpio10;
29 gpio10 = &gpio11;
30 gpio11 = &gpio12;
31 gpio12 = &gpio13;
32 mmc0 = &usdhc1;
33 serial0 = &lpuart1;
34 };
35
36 clocks {
37 osc: osc {
38 compatible = "fsl,imx-osc", "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <24000000>;
41 };
42
43 rcosc16M: rcosc16M {
44 compatible = "fsl,imx-osc", "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <16000000>;
47 };
48
49 osc32k: osc32k {
50 compatible = "fsl,imx-osc", "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <32768>;
53 };
54
55 };
56
57 soc {
58 semc: semc@400d4000 {
59 compatible = "fsl,imxrt-semc";
60 reg = <0x400d4000 0x4000>;
61 interrupts = <132>;
62 clocks = <&clks IMXRT1170_CLK_SEMC>;
63 pinctrl-0 = <&pinctrl_semc>;
64 pinctrl-names = "default";
65 status = "okay";
66 };
67
68 lpuart1: serial@4007c000 {
69 compatible = "fsl,imxrt-lpuart";
70 reg = <0x4007c000 0x4000>;
71 interrupts = <20>;
72 clocks = <&clks IMXRT1170_CLK_LPUART1>;
73 clock-names = "per";
74 status = "disabled";
75 };
76
77 iomuxc: iomuxc@400e8000 {
78 compatible = "fsl,imxrt-iomuxc";
79 reg = <0x400e8000 0x4000>;
80 fsl,mux_mask = <0x7>;
81 };
82
83 anatop: anatop@40c84000 {
84 compatible = "fsl,imxrt-anatop";
85 reg = <0x40c84000 0x4000>;
86 };
87
88 clks: ccm@40cc0000 {
89 compatible = "fsl,imxrt1170-ccm";
90 reg = <0x40cc0000 0x4000>;
91 #clock-cells = <1>;
92 };
93
94 usdhc1: usdhc@40418000 {
95 compatible = "fsl,imxrt-usdhc";
96 reg = <0x40418000 0x10000>;
97 interrupts = <133>;
98 clocks = <&clks IMXRT1170_CLK_USDHC1>;
99 clock-names = "per";
100 bus-width = <4>;
101 fsl,tuning-start-tap = <20>;
102 fsl,tuning-step= <2>;
103 status = "disabled";
104 };
105
106 gpio1: gpio@4012c000 {
107 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
108 reg = <0x4012c000 0x4000>;
109 interrupts = <100>,
110 <101>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116
117 gpio2: gpio@40130000 {
118 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
119 reg = <0x40130000 0x4000>;
120 interrupts = <102>,
121 <103>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 };
127
128 gpio3: gpio@40134000 {
129 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
130 reg = <0x40134000 0x4000>;
131 interrupts = <104>,
132 <105>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 };
138
139 gpio4: gpio@40138000 {
140 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
141 reg = <0x40138000 0x4000>;
142 interrupts = <106>,
143 <107>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <2>;
148 };
149
150 gpio5: gpio@4013c000 {
151 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
152 reg = <0x4013c000 0x4000>;
153 interrupts = <108>,
154 <109>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 };
160
161 gpio6: gpio@40140000 {
162 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
163 reg = <0x40140000 0x4000>;
164 interrupts = <61>,
165 <62>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio7: gpio@40c5c000 {
173 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
174 reg = <0x40c5c000 0x4000>;
175 interrupts = <99>,
176 <99>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
182
183 gpio8: gpio@40c60000 {
184 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
185 reg = <0x40c60000 0x4000>;
186 interrupts = <99>,
187 <99>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 };
193
194 gpio9: gpio@40c64000 {
195 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
196 reg = <0x40c64000 0x4000>;
197 interrupts = <99>,
198 <99>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 };
204
205 gpio10: gpio@40c68000 {
206 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
207 reg = <0x40c68000 0x4000>;
208 interrupts = <99>,
209 <99>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
216 gpio11: gpio@40c6c000 {
217 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
218 reg = <0x40c6c000 0x4000>;
219 interrupts = <99>,
220 <99>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
227 gpio12: gpio@40c70000 {
228 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
229 reg = <0x40c70000 0x4000>;
230 interrupts = <61>,
231 <62>; // only cm4
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 };
237
238 gpio13: gpio@40ca0000 {
239 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
240 reg = <0x40ca0000 0x4000>;
241 interrupts = <93>,
242 <93>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 };
248
249 gpt1: gpt1@400ec000 {
250 compatible = "fsl,imxrt-gpt";
251 reg = <0x400ec000 0x4000>;
252 interrupts = <119>;
253 clocks = <&clks IMXRT1170_CLK_GPT1>;
254 status = "disabled";
255 };
256 };
257};