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Patrice Chotard23a06412017-09-13 18:00:07 +02001/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02002 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotard23a06412017-09-13 18:00:07 +02004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <reset-uclass.h>
12#include <asm/io.h>
13
Patrick Delaunaya7519b32018-03-12 10:46:14 +010014/* reset clear offset for STM32MP RCC */
15#define RCC_CL 0x4
16
17enum rcc_type {
18 RCC_STM32 = 0,
19 RCC_STM32MP,
20};
Patrice Chotard23a06412017-09-13 18:00:07 +020021
22struct stm32_reset_priv {
23 fdt_addr_t base;
24};
25
26static int stm32_reset_request(struct reset_ctl *reset_ctl)
27{
28 return 0;
29}
30
31static int stm32_reset_free(struct reset_ctl *reset_ctl)
32{
33 return 0;
34}
35
36static int stm32_reset_assert(struct reset_ctl *reset_ctl)
37{
38 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
39 int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
40 int offset = reset_ctl->id % BITS_PER_LONG;
41 debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
42 reset_ctl->id, bank, offset);
43
Patrick Delaunaya7519b32018-03-12 10:46:14 +010044 if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
45 /* reset assert is done in rcc set register */
46 writel(BIT(offset), priv->base + bank);
47 else
48 setbits_le32(priv->base + bank, BIT(offset));
Patrice Chotard23a06412017-09-13 18:00:07 +020049
50 return 0;
51}
52
53static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
54{
55 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
56 int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
57 int offset = reset_ctl->id % BITS_PER_LONG;
58 debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
59 reset_ctl->id, bank, offset);
60
Patrick Delaunaya7519b32018-03-12 10:46:14 +010061 if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
62 /* reset deassert is done in rcc clr register */
63 writel(BIT(offset), priv->base + bank + RCC_CL);
64 else
65 clrbits_le32(priv->base + bank, BIT(offset));
Patrice Chotard23a06412017-09-13 18:00:07 +020066
67 return 0;
68}
69
70static const struct reset_ops stm32_reset_ops = {
71 .request = stm32_reset_request,
72 .free = stm32_reset_free,
73 .rst_assert = stm32_reset_assert,
74 .rst_deassert = stm32_reset_deassert,
75};
76
77static int stm32_reset_probe(struct udevice *dev)
78{
79 struct stm32_reset_priv *priv = dev_get_priv(dev);
80
Patrick Delaunaya7519b32018-03-12 10:46:14 +010081 priv->base = dev_read_addr(dev);
82 if (priv->base == FDT_ADDR_T_NONE) {
83 /* for MFD, get address of parent */
84 priv->base = dev_read_addr(dev->parent);
85 if (priv->base == FDT_ADDR_T_NONE)
86 return -EINVAL;
87 }
Patrice Chotard23a06412017-09-13 18:00:07 +020088
89 return 0;
90}
91
Patrick Delaunaya7519b32018-03-12 10:46:14 +010092static const struct udevice_id stm32_reset_ids[] = {
93 { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
94 { }
95};
96
Patrice Chotard23a06412017-09-13 18:00:07 +020097U_BOOT_DRIVER(stm32_rcc_reset) = {
98 .name = "stm32_rcc_reset",
99 .id = UCLASS_RESET,
Patrick Delaunaya7519b32018-03-12 10:46:14 +0100100 .of_match = stm32_reset_ids,
Patrice Chotard23a06412017-09-13 18:00:07 +0200101 .probe = stm32_reset_probe,
102 .priv_auto_alloc_size = sizeof(struct stm32_reset_priv),
103 .ops = &stm32_reset_ops,
104};