| Andre Przywara | 1ea4fac | 2016-05-12 12:14:41 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 ARM Ltd. |
| 3 | * |
| 4 | * ARM and ARM64 barrier instructions |
| 5 | * split from armv7.h to allow sharing between ARM and ARM64 |
| 6 | * |
| 7 | * Original copyright in armv7.h was: |
| 8 | * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com> |
| 9 | * |
| 10 | * Much of the original barrier code was contributed by: |
| 11 | * Valentine Barshak <valentine.barshak@cogentembedded.com> |
| 12 | * |
| 13 | * SPDX-License-Identifier: GPL-2.0+ |
| 14 | */ |
| 15 | #ifndef __BARRIERS_H__ |
| 16 | #define __BARRIERS_H__ |
| 17 | |
| 18 | #ifndef __ASSEMBLY__ |
| 19 | |
| 20 | #ifndef CONFIG_ARM64 |
| 21 | /* |
| 22 | * CP15 Barrier instructions |
| 23 | * Please note that we have separate barrier instructions in ARMv7 |
| 24 | * However, we use the CP15 based instructtions because we use |
| 25 | * -march=armv5 in U-Boot |
| 26 | */ |
| 27 | #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) |
| 28 | #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) |
| 29 | #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) |
| 30 | |
| 31 | #endif /* !CONFIG_ARM64 */ |
| 32 | |
| 33 | #if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) |
| 34 | #define ISB asm volatile ("isb sy" : : : "memory") |
| 35 | #define DSB asm volatile ("dsb sy" : : : "memory") |
| 36 | #define DMB asm volatile ("dmb sy" : : : "memory") |
| 37 | #else |
| 38 | #define ISB CP15ISB |
| 39 | #define DSB CP15DSB |
| 40 | #define DMB CP15DMB |
| 41 | #endif |
| 42 | |
| 43 | #endif /* __ASSEMBLY__ */ |
| 44 | #endif /* __BARRIERS_H__ */ |