| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Tom Rini | a2ac2b9 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| Peng Fan | abf8d96 | 2022-04-13 17:47:20 +0800 | [diff] [blame] | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 4 | CONFIG_ARCH_ROCKCHIP=y |
| Simon Glass | 9846390 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 5 | CONFIG_TEXT_BASE=0x00a00000 |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 8 | CONFIG_NR_DRAM_BANKS=2 |
| Tom Rini | fcb5117 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 9 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 10 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 |
| Tom Rini | 54c5c2b | 2022-01-24 21:08:41 +0000 | [diff] [blame] | 11 | CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 12 | CONFIG_ROCKCHIP_RK3568=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 13 | CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y |
| 14 | CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y |
| 15 | CONFIG_SPL_MMC=y |
| 16 | CONFIG_SPL_SERIAL=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 17 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 18 | CONFIG_TARGET_EVB_RK3568=y |
| Tom Rini | fcb5117 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 19 | CONFIG_SPL_STACK=0x400000 |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 20 | CONFIG_DEBUG_UART_BASE=0xFE660000 |
| 21 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| Tom Rini | 49c8ef0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 22 | CONFIG_SYS_LOAD_ADDR=0xc00800 |
| Tom Rini | d46e86d | 2022-04-08 13:36:51 -0400 | [diff] [blame] | 23 | CONFIG_DEBUG_UART=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 24 | CONFIG_FIT=y |
| 25 | CONFIG_FIT_VERBOSE=y |
| 26 | CONFIG_SPL_LOAD_FIT=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 27 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" |
| 28 | # CONFIG_DISPLAY_CPUINFO is not set |
| 29 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| Tom Rini | ca8a329 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 30 | CONFIG_SPL_MAX_SIZE=0x20000 |
| 31 | CONFIG_SPL_PAD_TO=0x7f8000 |
| Tom Rini | 6600b35 | 2022-05-27 10:19:45 -0400 | [diff] [blame] | 32 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 33 | CONFIG_SPL_BSS_START_ADDR=0x4000000 |
| Tom Rini | 9b5f9ae | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 34 | CONFIG_SPL_BSS_MAX_SIZE=0x4000 |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 35 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| Tom Rini | f113d7d | 2022-05-26 13:13:21 -0400 | [diff] [blame] | 36 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 37 | CONFIG_SPL_STACK_R=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 38 | CONFIG_SPL_ATF=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 39 | CONFIG_CMD_GPT=y |
| 40 | CONFIG_CMD_MMC=y |
| 41 | # CONFIG_CMD_SETEXPR is not set |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 42 | # CONFIG_SPL_DOS_PARTITION is not set |
| 43 | CONFIG_SPL_OF_CONTROL=y |
| 44 | CONFIG_OF_LIVE=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 45 | CONFIG_NET_RANDOM_ETHADDR=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 46 | CONFIG_SPL_REGMAP=y |
| 47 | CONFIG_SPL_SYSCON=y |
| 48 | CONFIG_SPL_CLK=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 49 | CONFIG_ROCKCHIP_GPIO=y |
| 50 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 51 | CONFIG_MISC=y |
| Tom Rini | d5bfef2 | 2021-12-11 14:55:53 -0500 | [diff] [blame] | 52 | CONFIG_SUPPORT_EMMC_RPMB=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 53 | CONFIG_MMC_DW=y |
| 54 | CONFIG_MMC_DW_ROCKCHIP=y |
| 55 | CONFIG_MMC_SDHCI=y |
| 56 | CONFIG_MMC_SDHCI_SDMA=y |
| 57 | CONFIG_MMC_SDHCI_ROCKCHIP=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 58 | CONFIG_ETH_DESIGNWARE=y |
| 59 | CONFIG_GMAC_ROCKCHIP=y |
| 60 | CONFIG_REGULATOR_PWM=y |
| 61 | CONFIG_PWM_ROCKCHIP=y |
| Nico Cheng | daec31e | 2021-10-26 10:42:19 +0800 | [diff] [blame] | 62 | CONFIG_SPL_RAM=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 63 | CONFIG_BAUDRATE=1500000 |
| 64 | CONFIG_DEBUG_UART_SHIFT=2 |
| Tom Rini | 9591b63 | 2022-12-04 09:39:03 -0500 | [diff] [blame] | 65 | CONFIG_SYS_NS16550_MEM32=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 66 | CONFIG_SYSRESET=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 67 | CONFIG_ERRNO_STR=y |