blob: 2f389dbe8df0a02ff2addfebad255388c5b1f699 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Raul Cardenas02000202015-02-27 11:22:06 -06002/*
3 * Copyright 2008-2015 Freescale Semiconductor, Inc.
Clement Faure859f4e02023-06-15 18:09:11 +08004 * Copyright 2022 NXP
Raul Cardenas02000202015-02-27 11:22:06 -06005 *
Raul Cardenas02000202015-02-27 11:22:06 -06006 * Command for encapsulating DEK blob
7 */
8
Tom Rinid678a592024-05-18 20:20:43 -06009#include <common.h>
Raul Cardenas02000202015-02-27 11:22:06 -060010#include <command.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Raul Cardenas02000202015-02-27 11:22:06 -060012#include <malloc.h>
Gaurav Jaincb5d0412022-03-24 11:50:33 +053013#include <memalign.h>
Raul Cardenas02000202015-02-27 11:22:06 -060014#include <asm/byteorder.h>
15#include <linux/compiler.h>
16#include <fsl_sec.h>
17#include <asm/arch/clock.h>
Ulises Cardenas98a49e52015-05-04 09:53:28 -050018#include <mapmem.h>
Clement Faure56d20502021-03-25 17:30:33 +080019#include <tee.h>
Clement Faure69f542c2021-03-25 17:30:34 +080020#ifdef CONFIG_IMX_SECO_DEK_ENCAP
Sean Andersonab121792023-10-14 16:47:44 -040021#include <imx_container.h>
Peng Fan99ac6c72023-04-28 12:08:09 +080022#include <firmware/imx/sci/sci.h>
Clement Faure69f542c2021-03-25 17:30:34 +080023#endif
Clement Faure859f4e02023-06-15 18:09:11 +080024#ifdef CONFIG_IMX_ELE_DEK_ENCAP
Sean Andersonab121792023-10-14 16:47:44 -040025#include <imx_container.h>
Clement Faure859f4e02023-06-15 18:09:11 +080026#include <asm/mach-imx/ele_api.h>
Clement Faure859f4e02023-06-15 18:09:11 +080027#endif
28
Clement Faure69f542c2021-03-25 17:30:34 +080029#include <cpu_func.h>
Raul Cardenas02000202015-02-27 11:22:06 -060030
Raul Cardenas02000202015-02-27 11:22:06 -060031/**
32* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
33* @src: - Address of data to be encapsulated
34* @dst: - Desination address of encapsulated data
35* @len: - Size of data to be encapsulated
36*
37* Returns zero on success,and negative on error.
38*/
Clement Faure56d20502021-03-25 17:30:33 +080039#ifdef CONFIG_IMX_CAAM_DEK_ENCAP
40static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
Raul Cardenas02000202015-02-27 11:22:06 -060041{
Clement Faure56d20502021-03-25 17:30:33 +080042 u8 *src_ptr, *dst_ptr;
43
44 src_ptr = map_sysmem(src_addr, len / 8);
45 dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len / 8));
Raul Cardenas02000202015-02-27 11:22:06 -060046
Breno Lima6d7b2702021-03-25 17:30:04 +080047 hab_caam_clock_enable(1);
48
Tom Rini6cc04542022-10-28 20:27:13 -040049 u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
Breno Lima8c497e12021-03-25 17:30:03 +080050 FSL_CAAM_ORSR_JRa_OFFSET);
Breno Lima55086e12021-03-25 17:30:05 +080051 if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
Raul Cardenas02000202015-02-27 11:22:06 -060052 sec_init();
Raul Cardenas02000202015-02-27 11:22:06 -060053
54 if (!((len == 128) | (len == 192) | (len == 256))) {
55 debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
56 return -1;
57 }
58
59 len /= 8;
Clement Faure56d20502021-03-25 17:30:33 +080060 return blob_dek(src_ptr, dst_ptr, len);
61}
62#endif /* CONFIG_IMX_CAAM_DEK_ENCAP */
63
64#ifdef CONFIG_IMX_OPTEE_DEK_ENCAP
65
66#define PTA_DEK_BLOB_PTA_UUID {0xef477737, 0x0db1, 0x4a9d, \
67 {0x84, 0x37, 0xf2, 0xf5, 0x35, 0xc0, 0xbd, 0x92} }
68
69#define OPTEE_BLOB_HDR_SIZE 8
70
71static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
72{
73 struct udevice *dev = NULL;
74 struct tee_shm *shm_input, *shm_output;
75 struct tee_open_session_arg arg = {0};
76 struct tee_invoke_arg arg_func = {0};
77 const struct tee_optee_ta_uuid uuid = PTA_DEK_BLOB_PTA_UUID;
78 struct tee_param param[4] = {0};
79 int ret;
80
81 /* Get tee device */
82 dev = tee_find_device(NULL, NULL, NULL, NULL);
83 if (!dev) {
84 printf("Cannot get OP-TEE device\n");
85 return -1;
86 }
87
88 /* Set TA UUID */
89 tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
90
91 /* Open TA session */
92 ret = tee_open_session(dev, &arg, 0, NULL);
93 if (ret < 0) {
94 printf("Cannot open session with PTA Blob 0x%X\n", ret);
95 return -1;
96 }
97
98 /* Allocate shared input and output buffers for TA */
99 ret = tee_shm_register(dev, (void *)(ulong)src_addr, len / 8, 0x0, &shm_input);
100 if (ret < 0) {
101 printf("Cannot register input shared memory 0x%X\n", ret);
102 goto error;
103 }
104
105 ret = tee_shm_register(dev, (void *)(ulong)dst_addr,
106 BLOB_SIZE(len / 8) + OPTEE_BLOB_HDR_SIZE,
107 0x0, &shm_output);
108 if (ret < 0) {
109 printf("Cannot register output shared memory 0x%X\n", ret);
Ye Lif0e974e2023-06-15 18:09:10 +0800110 tee_shm_free(shm_input);
Clement Faure56d20502021-03-25 17:30:33 +0800111 goto error;
112 }
113
114 param[0].u.memref.shm = shm_input;
115 param[0].u.memref.size = shm_input->size;
116 param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
117 param[1].u.memref.shm = shm_output;
118 param[1].u.memref.size = shm_output->size;
119 param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
120 param[2].attr = TEE_PARAM_ATTR_TYPE_NONE;
121 param[3].attr = TEE_PARAM_ATTR_TYPE_NONE;
122
123 arg_func.func = 0;
124 arg_func.session = arg.session;
125
126 /* Generate DEK blob */
127 arg_func.session = arg.session;
128 ret = tee_invoke_func(dev, &arg_func, 4, param);
129 if (ret < 0)
130 printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);
131
Clement Faure56d20502021-03-25 17:30:33 +0800132 /* Free shared memory */
133 tee_shm_free(shm_input);
134 tee_shm_free(shm_output);
135
Ye Lif0e974e2023-06-15 18:09:10 +0800136error:
Clement Faure56d20502021-03-25 17:30:33 +0800137 /* Close session */
138 ret = tee_close_session(dev, arg.session);
139 if (ret < 0)
140 printf("Cannot close session with PTA DEK Blob 0x%X\n", ret);
Raul Cardenas02000202015-02-27 11:22:06 -0600141
142 return ret;
143}
Clement Faure56d20502021-03-25 17:30:33 +0800144#endif /* CONFIG_IMX_OPTEE_DEK_ENCAP */
Clement Faure69f542c2021-03-25 17:30:34 +0800145#ifdef CONFIG_IMX_SECO_DEK_ENCAP
146
147#define DEK_BLOB_KEY_ID 0x0
148
149#define AHAB_PRIVATE_KEY 0x81
150#define AHAB_VERSION 0x00
151#define AHAB_MODE_CBC 0x67
152#define AHAB_ALG_AES 0x55
153#define AHAB_128_AES_KEY 0x10
154#define AHAB_192_AES_KEY 0x18
155#define AHAB_256_AES_KEY 0x20
156#define AHAB_FLAG_KEK 0x80
157#define AHAB_DEK_BLOB 0x01
158
159#define DEK_BLOB_HDR_SIZE 8
160#define SECO_PT 2U
161
162static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
163{
Peng Fandd654ca2023-06-15 18:08:58 +0800164 int err;
Clement Faure69f542c2021-03-25 17:30:34 +0800165 sc_rm_mr_t mr_input, mr_output;
166 struct generate_key_blob_hdr hdr;
167 u8 in_size, out_size;
168 u8 *src_ptr, *dst_ptr;
169 int ret = 0;
170 int i;
171
172 /* Set sizes */
173 in_size = sizeof(struct generate_key_blob_hdr) + len / 8;
174 out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE;
175
176 /* Get src and dst virtual addresses */
177 src_ptr = map_sysmem(src_addr, in_size);
178 dst_ptr = map_sysmem(dst_addr, out_size);
179
180 /* Check addr input */
181 if (!(src_ptr && dst_ptr)) {
182 debug("src_addr or dst_addr invalid\n");
183 return -1;
184 }
185
186 /* Build key header */
187 hdr.version = AHAB_VERSION;
188 hdr.length_lsb = sizeof(struct generate_key_blob_hdr) + len / 8;
189 hdr.length_msb = 0x00;
190 hdr.tag = AHAB_PRIVATE_KEY;
191 hdr.flags = AHAB_DEK_BLOB;
192 hdr.algorithm = AHAB_ALG_AES;
193 hdr.mode = AHAB_MODE_CBC;
194
195 switch (len) {
196 case 128:
197 hdr.size = AHAB_128_AES_KEY;
198 break;
199 case 192:
200 hdr.size = AHAB_192_AES_KEY;
201 break;
202 case 256:
203 hdr.size = AHAB_256_AES_KEY;
204 break;
205 default:
206 /* Not supported */
207 debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
208 return -1;
209 }
210
211 /* Build input message */
212 memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)),
213 (void *)src_ptr, len / 8);
214 memcpy((void *)src_ptr, (void *)&hdr,
215 sizeof(struct generate_key_blob_hdr));
216
217 /* Flush the cache before triggering the CAAM DMA */
218 flush_dcache_range(src_addr, src_addr + in_size);
219
220 /* Find input memory region */
221 err = sc_rm_find_memreg((-1), &mr_input, src_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
222 ALIGN(src_addr + in_size, CONFIG_SYS_CACHELINE_SIZE));
223 if (err) {
224 printf("Error: find memory region 0x%X\n", src_addr);
225 return -ENOMEM;
226 }
227
228 /* Find output memory region */
229 err = sc_rm_find_memreg((-1), &mr_output, dst_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
230 ALIGN(dst_addr + out_size, CONFIG_SYS_CACHELINE_SIZE));
231 if (err) {
232 printf("Error: find memory region 0x%X\n", dst_addr);
233 return -ENOMEM;
234 }
235
236 /* Set memory region permissions for SECO */
237 err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT,
238 SC_RM_PERM_FULL);
239 if (err) {
240 printf("Set permission failed for input memory region\n");
241 ret = -EPERM;
242 goto error;
243 }
244
245 err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT,
246 SC_RM_PERM_FULL);
247 if (err) {
248 printf("Set permission failed for output memory region\n");
249 ret = -EPERM;
250 goto error;
251 }
252
253 /* Flush output data before SECO operation */
254 flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
255 roundup(out_size, ARCH_DMA_MINALIGN)));
256
257 /* Generate DEK blob */
258 err = sc_seco_gen_key_blob((-1), 0x0, src_addr, dst_addr, out_size);
259 if (err) {
260 ret = -EPERM;
261 goto error;
262 }
263
264 /* Invalidate output buffer */
265 invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
266 roundup(out_size, ARCH_DMA_MINALIGN)));
267
268 printf("DEK Blob\n");
269 for (i = 0; i < DEK_BLOB_HDR_SIZE + BLOB_SIZE(len / 8); i++)
270 printf("%02X", dst_ptr[i]);
271 printf("\n");
272
273error:
274 /* Remove memory region permission to SECO */
275 err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT,
276 SC_RM_PERM_NONE);
277 if (err) {
278 printf("Error: remove permission failed for input\n");
279 ret = -EPERM;
280 }
281
282 err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT,
283 SC_RM_PERM_NONE);
284 if (err) {
285 printf("Error: remove permission failed for output\n");
286 ret = -EPERM;
287 }
288
289 return ret;
290}
291#endif /* CONFIG_IMX_SECO_DEK_ENCAP */
Raul Cardenas02000202015-02-27 11:22:06 -0600292
Clement Faure859f4e02023-06-15 18:09:11 +0800293#ifdef CONFIG_IMX_ELE_DEK_ENCAP
294
295#define DEK_BLOB_HDR_SIZE 8
296#define AHAB_PRIVATE_KEY 0x81
297#define AHAB_DEK_BLOB 0x01
298#define AHAB_ALG_AES 0x03
299#define AHAB_128_AES_KEY 0x10
300#define AHAB_192_AES_KEY 0x18
301#define AHAB_256_AES_KEY 0x20
302
303static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
304{
305 u8 in_size, out_size;
306 u8 *src_ptr, *dst_ptr;
307 struct generate_key_blob_hdr hdr;
308
309 /* Set sizes */
310 in_size = sizeof(struct generate_key_blob_hdr) + len / 8;
311 out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE;
312
313 /* Get src and dst virtual addresses */
314 src_ptr = map_sysmem(src_addr, in_size);
315 dst_ptr = map_sysmem(dst_addr, out_size);
316
317 /* Check addr input */
318 if (!(src_ptr && dst_ptr)) {
319 debug("src_addr or dst_addr invalid\n");
320 return -1;
321 }
322
323 /* Build key header */
324 hdr.version = 0x0;
325 hdr.length_lsb = in_size;
326 hdr.length_msb = 0x00;
327 hdr.tag = AHAB_PRIVATE_KEY;
328 hdr.flags = AHAB_DEK_BLOB;
329 hdr.algorithm = AHAB_ALG_AES;
330 hdr.mode = 0x0; /* Not used by the ELE */
331
332 switch (len) {
333 case 128:
334 hdr.size = AHAB_128_AES_KEY;
335 break;
336 case 192:
337 hdr.size = AHAB_192_AES_KEY;
338 break;
339 case 256:
340 hdr.size = AHAB_256_AES_KEY;
341 break;
342 default:
343 /* Not supported */
344 debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
345 return -1;
346 }
347
348 /* Move input key and append blob header */
349 memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)),
350 (void *)src_ptr, len / 8);
351 memcpy((void *)src_ptr, (void *)&hdr,
352 sizeof(struct generate_key_blob_hdr));
353
354 /* Flush the cache */
355 flush_dcache_range(src_addr, src_addr + in_size);
356 flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
357 roundup(out_size, ARCH_DMA_MINALIGN)));
358
359 /* Call ELE */
360 if (ele_generate_dek_blob(0x00, src_addr, dst_addr, out_size))
361 return -1;
362
363 /* Invalidate output buffer */
364 invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
365 roundup(out_size, ARCH_DMA_MINALIGN)));
366
367 return 0;
368}
369#endif /* CONFIG_IMX_ELE_DEK_ENCAP */
370
Raul Cardenas02000202015-02-27 11:22:06 -0600371/**
372 * do_dek_blob() - Handle the "dek_blob" command-line command
373 * @cmdtp: Command data struct pointer
374 * @flag: Command flag
375 * @argc: Command-line argument count
376 * @argv: Array of command-line arguments
377 *
378 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
379 * on error.
380 */
Simon Glass09140112020-05-10 11:40:03 -0600381static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc,
382 char *const argv[])
Raul Cardenas02000202015-02-27 11:22:06 -0600383{
384 uint32_t src_addr, dst_addr, len;
Raul Cardenas02000202015-02-27 11:22:06 -0600385
386 if (argc != 4)
387 return CMD_RET_USAGE;
388
Simon Glass7e5f4602021-07-24 09:03:29 -0600389 src_addr = hextoul(argv[1], NULL);
390 dst_addr = hextoul(argv[2], NULL);
Simon Glass0b1284e2021-07-24 09:03:30 -0600391 len = dectoul(argv[3], NULL);
Raul Cardenas02000202015-02-27 11:22:06 -0600392
Clement Faure56d20502021-03-25 17:30:33 +0800393 return blob_encap_dek(src_addr, dst_addr, len);
Raul Cardenas02000202015-02-27 11:22:06 -0600394}
395
396/***************************************************/
397static char dek_blob_help_text[] =
398 "src dst len - Encapsulate and create blob of data\n"
399 " $len bits long at address $src and\n"
400 " store the result at address $dst.\n";
401
402U_BOOT_CMD(
403 dek_blob, 4, 1, do_dek_blob,
404 "Data Encryption Key blob encapsulation",
405 dek_blob_help_text
406);