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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a8c97f4a00fb5a9a31970351fce4355d37d19c7d / . / arch / arm / dts / stm32mp15-ddr.dtsi
blob: 2a139c54e902a468e436179c5bc86e81e012262d [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]2/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]4 */
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]5#include <linux/stringify.h>
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]6
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]7&ddr {
8 config-DDR_MEM_COMPATIBLE {
9 u-boot,dm-pre-reloc;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]10
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]11 compatible = __stringify(st,DDR_MEM_COMPATIBLE);
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]12
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]13 st,mem-name = DDR_MEM_NAME;
14 st,mem-speed = <DDR_MEM_SPEED>;
15 st,mem-size = <DDR_MEM_SIZE>;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]16
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]17 st,ctl-reg = <
18 DDR_MSTR
19 DDR_MRCTRL0
20 DDR_MRCTRL1
21 DDR_DERATEEN
22 DDR_DERATEINT
23 DDR_PWRCTL
24 DDR_PWRTMG
25 DDR_HWLPCTL
26 DDR_RFSHCTL0
27 DDR_RFSHCTL3
28 DDR_CRCPARCTL0
29 DDR_ZQCTL0
30 DDR_DFITMG0
31 DDR_DFITMG1
32 DDR_DFILPCFG0
33 DDR_DFIUPD0
34 DDR_DFIUPD1
35 DDR_DFIUPD2
36 DDR_DFIPHYMSTR
37 DDR_ODTMAP
38 DDR_DBG0
39 DDR_DBG1
40 DDR_DBGCMD
41 DDR_POISONCFG
42 DDR_PCCFG
43 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]44
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]45 st,ctl-timing = <
46 DDR_RFSHTMG
47 DDR_DRAMTMG0
48 DDR_DRAMTMG1
49 DDR_DRAMTMG2
50 DDR_DRAMTMG3
51 DDR_DRAMTMG4
52 DDR_DRAMTMG5
53 DDR_DRAMTMG6
54 DDR_DRAMTMG7
55 DDR_DRAMTMG8
56 DDR_DRAMTMG14
57 DDR_ODTCFG
58 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]59
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]60 st,ctl-map = <
61 DDR_ADDRMAP1
62 DDR_ADDRMAP2
63 DDR_ADDRMAP3
64 DDR_ADDRMAP4
65 DDR_ADDRMAP5
66 DDR_ADDRMAP6
67 DDR_ADDRMAP9
68 DDR_ADDRMAP10
69 DDR_ADDRMAP11
70 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]71
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]72 st,ctl-perf = <
73 DDR_SCHED
74 DDR_SCHED1
75 DDR_PERFHPR1
76 DDR_PERFLPR1
77 DDR_PERFWR1
78 DDR_PCFGR_0
79 DDR_PCFGW_0
80 DDR_PCFGQOS0_0
81 DDR_PCFGQOS1_0
82 DDR_PCFGWQOS0_0
83 DDR_PCFGWQOS1_0
84 DDR_PCFGR_1
85 DDR_PCFGW_1
86 DDR_PCFGQOS0_1
87 DDR_PCFGQOS1_1
88 DDR_PCFGWQOS0_1
89 DDR_PCFGWQOS1_1
90 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]91
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]92 st,phy-reg = <
93 DDR_PGCR
94 DDR_ACIOCR
95 DDR_DXCCR
96 DDR_DSGCR
97 DDR_DCR
98 DDR_ODTCR
99 DDR_ZQ0CR1
100 DDR_DX0GCR
101 DDR_DX1GCR
102 DDR_DX2GCR
103 DDR_DX3GCR
104 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]105
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]106 st,phy-timing = <
107 DDR_PTR0
108 DDR_PTR1
109 DDR_PTR2
110 DDR_DTPR0
111 DDR_DTPR1
112 DDR_DTPR2
113 DDR_MR0
114 DDR_MR1
115 DDR_MR2
116 DDR_MR3
117 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]118
Patrick Delaunay9368bdf2020-03-06 11:14:11 +0100[diff] [blame]119#ifdef DDR_PHY_CAL_SKIP
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]120 st,phy-cal = <
121 DDR_DX0DLLCR
122 DDR_DX0DQTR
123 DDR_DX0DQSTR
124 DDR_DX1DLLCR
125 DDR_DX1DQTR
126 DDR_DX1DQSTR
127 DDR_DX2DLLCR
128 DDR_DX2DQTR
129 DDR_DX2DQSTR
130 DDR_DX3DLLCR
131 DDR_DX3DQTR
132 DDR_DX3DQSTR
133 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]134
Patrick Delaunay9368bdf2020-03-06 11:14:11 +0100[diff] [blame]135#endif
136
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]137 status = "okay";
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]138 };
139};
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame^]140
141#undef DDR_MEM_COMPATIBLE
142#undef DDR_MEM_NAME
143#undef DDR_MEM_SPEED
144#undef DDR_MEM_SIZE
145
146#undef DDR_MSTR
147#undef DDR_MRCTRL0
148#undef DDR_MRCTRL1
149#undef DDR_DERATEEN
150#undef DDR_DERATEINT
151#undef DDR_PWRCTL
152#undef DDR_PWRTMG
153#undef DDR_HWLPCTL
154#undef DDR_RFSHCTL0
155#undef DDR_RFSHCTL3
156#undef DDR_RFSHTMG
157#undef DDR_CRCPARCTL0
158#undef DDR_DRAMTMG0
159#undef DDR_DRAMTMG1
160#undef DDR_DRAMTMG2
161#undef DDR_DRAMTMG3
162#undef DDR_DRAMTMG4
163#undef DDR_DRAMTMG5
164#undef DDR_DRAMTMG6
165#undef DDR_DRAMTMG7
166#undef DDR_DRAMTMG8
167#undef DDR_DRAMTMG14
168#undef DDR_ZQCTL0
169#undef DDR_DFITMG0
170#undef DDR_DFITMG1
171#undef DDR_DFILPCFG0
172#undef DDR_DFIUPD0
173#undef DDR_DFIUPD1
174#undef DDR_DFIUPD2
175#undef DDR_DFIPHYMSTR
176#undef DDR_ADDRMAP1
177#undef DDR_ADDRMAP2
178#undef DDR_ADDRMAP3
179#undef DDR_ADDRMAP4
180#undef DDR_ADDRMAP5
181#undef DDR_ADDRMAP6
182#undef DDR_ADDRMAP9
183#undef DDR_ADDRMAP10
184#undef DDR_ADDRMAP11
185#undef DDR_ODTCFG
186#undef DDR_ODTMAP
187#undef DDR_SCHED
188#undef DDR_SCHED1
189#undef DDR_PERFHPR1
190#undef DDR_PERFLPR1
191#undef DDR_PERFWR1
192#undef DDR_DBG0
193#undef DDR_DBG1
194#undef DDR_DBGCMD
195#undef DDR_POISONCFG
196#undef DDR_PCCFG
197#undef DDR_PCFGR_0
198#undef DDR_PCFGW_0
199#undef DDR_PCFGQOS0_0
200#undef DDR_PCFGQOS1_0
201#undef DDR_PCFGWQOS0_0
202#undef DDR_PCFGWQOS1_0
203#undef DDR_PCFGR_1
204#undef DDR_PCFGW_1
205#undef DDR_PCFGQOS0_1
206#undef DDR_PCFGQOS1_1
207#undef DDR_PCFGWQOS0_1
208#undef DDR_PCFGWQOS1_1
209#undef DDR_PGCR
210#undef DDR_PTR0
211#undef DDR_PTR1
212#undef DDR_PTR2
213#undef DDR_ACIOCR
214#undef DDR_DXCCR
215#undef DDR_DSGCR
216#undef DDR_DCR
217#undef DDR_DTPR0
218#undef DDR_DTPR1
219#undef DDR_DTPR2
220#undef DDR_MR0
221#undef DDR_MR1
222#undef DDR_MR2
223#undef DDR_MR3
224#undef DDR_ODTCR
225#undef DDR_ZQ0CR1
226#undef DDR_DX0GCR
227#undef DDR_DX0DLLCR
228#undef DDR_DX0DQTR
229#undef DDR_DX0DQSTR
230#undef DDR_DX1GCR
231#undef DDR_DX1DLLCR
232#undef DDR_DX1DQTR
233#undef DDR_DX1DQSTR
234#undef DDR_DX2GCR
235#undef DDR_DX2DLLCR
236#undef DDR_DX2DQTR
237#undef DDR_DX2DQSTR
238#undef DDR_DX3GCR
239#undef DDR_DX3DLLCR
240#undef DDR_DX3DQTR
241#undef DDR_DX3DQSTR