Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration settings for the SAMA5D4EK board. |
| 4 | * |
| 5 | * Copyright (C) 2014 Atmel |
| 6 | * Bo Shen <voice.shen@atmel.com> |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H |
| 10 | #define __CONFIG_H |
| 11 | |
Wu, Josh | b2d387b | 2015-03-30 14:51:19 +0800 | [diff] [blame] | 12 | #include "at91-sama5_common.h" |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 13 | |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 14 | /* SDRAM */ |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 15 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 16 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 |
| 17 | |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 18 | #ifdef CONFIG_SPL_BUILD |
Wenyou Yang | ef33aa3 | 2017-04-13 10:31:19 +0800 | [diff] [blame] | 19 | #define CONFIG_SYS_INIT_SP_ADDR 0x218000 |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 20 | #else |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 21 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | ef33aa3 | 2017-04-13 10:31:19 +0800 | [diff] [blame] | 22 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 23 | #endif |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 24 | |
| 25 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 26 | |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 27 | /* NAND flash */ |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 28 | #ifdef CONFIG_CMD_NAND |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 29 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Wenyou Yang | e61ed48 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 30 | #define CONFIG_SYS_NAND_BASE 0x80000000 |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 31 | /* our ALE is AD21 */ |
| 32 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 33 | /* our CLE is AD22 */ |
| 34 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 35 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 36 | #endif |
| 37 | |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 38 | /* SPL */ |
Wenyou Yang | ef33aa3 | 2017-04-13 10:31:19 +0800 | [diff] [blame] | 39 | #define CONFIG_SPL_MAX_SIZE 0x18000 |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 40 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 41 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 42 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 43 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 44 | |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 45 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 46 | |
Wenyou Yang | 5541543 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 47 | #ifdef CONFIG_SD_BOOT |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 48 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
| 49 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 50 | |
Wenyou Yang | 5541543 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 51 | #elif CONFIG_SPI_BOOT |
Wenyou Yang | 5541543 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 52 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 |
| 53 | |
| 54 | #elif CONFIG_NAND_BOOT |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 55 | #define CONFIG_SPL_NAND_DRIVERS |
| 56 | #define CONFIG_SPL_NAND_BASE |
Wenyou Yang | 5541543 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 57 | #endif |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 58 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
| 59 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 60 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 |
| 61 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 62 | #define CONFIG_SYS_NAND_OOBSIZE 224 |
| 63 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 |
| 64 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
Bo Shen | 5a4c9c2 | 2014-12-15 13:24:38 +0800 | [diff] [blame] | 65 | |
Bo Shen | 927b901 | 2014-11-10 15:24:02 +0800 | [diff] [blame] | 66 | #endif |