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Stefan Roese1eac2a72006-11-29 15:42:37 +01001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Based on original work by
6 * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/************************************************************************
28 * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
29 *
30 * The defines:
31 * CONFIG_P3M750 or
32 * CONFIG_P3M7448
33 * are written into include/config.h by the "make xxx_config" command
34 ***********************************************************************/
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/*-----------------------------------------------------------------------
39 * High Level Configuration Options
40 *----------------------------------------------------------------------*/
41#define CONFIG_P3Mx /* used for both board versions */
42
43#if defined (CONFIG_P3M750)
44#define CONFIG_750FX /* 750GL/GX/FX */
Becky Bruce31d82672008-05-08 19:02:12 -050045#define CONFIG_HIGH_BATS /* High BATs supported */
Stefan Roese1eac2a72006-11-29 15:42:37 +010046#define CFG_BOARD_NAME "P3M750"
47#define CFG_BUS_HZ 100000000
48#define CFG_BUS_CLK CFG_BUS_HZ
49#define CFG_TCLK 100000000
50#elif defined (CONFIG_P3M7448)
51#define CONFIG_74xx
52#define CFG_BOARD_NAME "P3M7448"
53#define CFG_BUS_HZ 133333333
54#define CFG_BUS_CLK CFG_BUS_HZ
55#define CFG_TCLK 133333333
56#endif
57#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
58
59/* which initialization functions to call for this board */
60#define CFG_BOARD_ASM_INIT 1
61#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
62#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */
63#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
Stefan Roese1eac2a72006-11-29 15:42:37 +010064
65/*-----------------------------------------------------------------------
66 * Base addresses -- Note these are effective addresses where the
67 * actual resources get mapped (not physical addresses)
68 *----------------------------------------------------------------------*/
69#define CFG_SDRAM_BASE 0x00000000
70#ifdef CONFIG_P3M750
71#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
72#endif
73
74#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
75#if defined (CONFIG_P3M750)
76#define CFG_FLASH_BASE 0xff800000 /* start of flash banks */
77#define CFG_BOOT_SIZE _8M /* boot flash */
78#elif defined (CONFIG_P3M7448)
79#define CFG_FLASH_BASE 0xff000000 /* start of flash banks */
80#define CFG_BOOT_SIZE _16M /* boot flash */
81#endif
82#define CFG_BOOT_SPACE CFG_FLASH_BASE /* BOOT_CS0 flash 0 */
83#define CFG_MONITOR_BASE 0xfff00000
84#define CFG_RESET_ADDRESS 0xfff00100
85#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
86#define CFG_MISC_REGION_BASE 0xf0000000
87
88#define CFG_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
89#define CFG_GT_REGS 0xf1000000 /* GT Registers are mapped here */
90#define CFG_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
91
92/*-----------------------------------------------------------------------
93 * Initial RAM & stack pointer (placed in internal SRAM)
94 *----------------------------------------------------------------------*/
95 /*
96 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
97 * To an unused memory region. The stack will remain in cache until RAM
98 * is initialized
99*/
100#undef CFG_INIT_RAM_LOCK
101#define CFG_INIT_RAM_ADDR 0x42000000
102#define CFG_INIT_RAM_END 0x1000
103#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
104#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
105
106
107/*-----------------------------------------------------------------------
108 * Serial Port
109 *----------------------------------------------------------------------*/
110#define CONFIG_MPSC /* MV64460 Serial */
111#define CONFIG_MPSC_PORT 0
112#define CONFIG_BAUDRATE 115200 /* console baudrate */
113#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
114#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
115#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
116
117/*-----------------------------------------------------------------------
118 * Ethernet
119 *----------------------------------------------------------------------*/
120/* Change the default ethernet port, use this define (options: 0, 1, 2) */
121#define CFG_ETH_PORT ETH_0
122#define CONFIG_NET_MULTI
123#define MV_ETH_DEVS 2
124#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
125#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
126
127/*-----------------------------------------------------------------------
128 * FLASH related
129 *----------------------------------------------------------------------*/
130#define CFG_FLASH_CFI /* The flash is CFI compatible */
131#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
132#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
133#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
134#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
136#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
137#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
138#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
139
140#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
141#if defined (CONFIG_P3M750)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200142#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100143#elif defined (CONFIG_P3M7448)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200144#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100145#endif
146#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
147#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
148
149/*-----------------------------------------------------------------------
150 * DDR SDRAM
151 *----------------------------------------------------------------------*/
152#define CONFIG_MV64460_ECC
153
154/*-----------------------------------------------------------------------
155 * I2C
156 *----------------------------------------------------------------------*/
157#define CFG_I2C_SPEED 100000 /* I2C speed default */
158
159/* I2C RTC */
160#define CONFIG_RTC_M41T11 1
161#define CFG_I2C_RTC_ADDR 0x68
162#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
163
164/*-----------------------------------------------------------------------
165 * PCI stuff
166 *----------------------------------------------------------------------*/
167#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
168#define PCI_HOST_FORCE 1 /* configure as pci host */
169#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
170
Stefan Roese0057d752007-01-18 11:54:52 +0100171#undef CONFIG_PCI /* include pci support */
172#ifdef CONFIG_PCI
Stefan Roese1eac2a72006-11-29 15:42:37 +0100173#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
174#define CONFIG_PCI_PNP /* do pci plug-and-play */
175#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
Stefan Roese0057d752007-01-18 11:54:52 +0100176#endif /* CONFIG_PCI */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100177
178/* PCI MEMORY MAP section */
179#define CFG_PCI0_MEM_BASE 0x80000000
180#define CFG_PCI0_MEM_SIZE _128M
181#define CFG_PCI1_MEM_BASE 0x88000000
182#define CFG_PCI1_MEM_SIZE _128M
183
184#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
185#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
186
187/* PCI I/O MAP section */
188#define CFG_PCI0_IO_BASE 0xfa000000
189#define CFG_PCI0_IO_SIZE _16M
190#define CFG_PCI1_IO_BASE 0xfb000000
191#define CFG_PCI1_IO_SIZE _16M
192
193#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
194#define CFG_PCI0_IO_SPACE_PCI 0x00000000
195#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
196#define CFG_PCI1_IO_SPACE_PCI 0x00000000
197
198#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
Stefan Roese1eac2a72006-11-29 15:42:37 +0100199#define CFG_PCI_IDSEL 0x30
200
201#undef CONFIG_BOOTARGS
202#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
203 "netdev=eth0\0" \
204 "nfsargs=setenv bootargs root=/dev/nfs rw " \
205 "nfsroot=${serverip}:${rootpath}\0" \
206 "ramargs=setenv bootargs root=/dev/ram rw\0" \
207 "addip=setenv bootargs ${bootargs} " \
208 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
209 ":${hostname}:${netdev}:off panic=1\0" \
210 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
211 "flash_nfs=run nfsargs addip addtty;" \
212 "bootm ${kernel_addr}\0" \
213 "flash_self=run ramargs addip addtty;" \
214 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
215 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
216 "bootm\0" \
217 "rootpath=/opt/eldk/ppc_6xx\0" \
218 "u-boot=p3mx/u-boot/u-boot.bin\0" \
219 "load=tftp 100000 ${u-boot}\0" \
220 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
221 "cp.b 100000 fff00000 40000;" \
222 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100223 "upd=run load update\0" \
Stefan Roese1eac2a72006-11-29 15:42:37 +0100224 "serverip=11.0.0.152\0"
225
226#if defined (CONFIG_P3M750)
227#define CONFIG_EXTRA_ENV_SETTINGS \
228 CONFIG_EXTRA_ENV_SETTINGS_COMMON \
229 "hostname=p3m750\0" \
230 "bootfile=/tftpboot/p3mx/vxWorks.st\0" \
231 "kernel_addr=fc000000\0" \
232 "ramdisk_addr=fc180000\0" \
233 "vxfile=p3m750/vxWorks\0" \
234 "vxuser=ddg\0" \
235 "vxpass=ddg\0" \
236 "vxtarget=target\0" \
237 "vxflags=0x8\0" \
238 "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
239 "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
240 "f=${vxflags}\0"
241#elif defined (CONFIG_P3M7448)
242#define CONFIG_EXTRA_ENV_SETTINGS \
243 CONFIG_EXTRA_ENV_SETTINGS_COMMON \
244 "hostname=p3m7448\0"
245#endif
246
247#if defined (CONFIG_P3M750)
248#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
249#elif defined (CONFIG_P3M7448)
250#define CONFIG_BOOTCOMMAND " "
251#endif
252
253#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500254
255/*
256 * BOOTP options
257 */
258#define CONFIG_BOOTP_SUBNETMASK
259#define CONFIG_BOOTP_GATEWAY
260#define CONFIG_BOOTP_HOSTNAME
261#define CONFIG_BOOTP_BOOTPATH
262#define CONFIG_BOOTP_BOOTFILESIZE
Stefan Roese1eac2a72006-11-29 15:42:37 +0100263
Jon Loeliger26a34562007-07-04 22:33:17 -0500264/*
265 * Command line configuration.
266 */
267#include <config_cmd_default.h>
268
269#define CONFIG_CMD_ASKENV
270#define CONFIG_CMD_DATE
271#define CONFIG_CMD_DIAG
272#define CONFIG_CMD_ELF
273#define CONFIG_CMD_I2C
274#define CONFIG_CMD_IRQ
275#define CONFIG_CMD_MII
276#define CONFIG_CMD_NET
277#define CONFIG_CMD_NFS
278#define CONFIG_CMD_PING
279#define CONFIG_CMD_REGINFO
280#define CONFIG_CMD_PCI
281#define CONFIG_CMD_CACHE
282#define CONFIG_CMD_SDRAM
283
Stefan Roese1eac2a72006-11-29 15:42:37 +0100284
285/*-----------------------------------------------------------------------
286 * Miscellaneous configurable options
287 *----------------------------------------------------------------------*/
288#define CFG_HUSH_PARSER
289#define CFG_PROMPT_HUSH_PS2 "> "
290
291#define CFG_LONGHELP /* undef to save memory */
292#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger26a34562007-07-04 22:33:17 -0500293#if defined(CONFIG_CMD_KGDB)
Stefan Roese1eac2a72006-11-29 15:42:37 +0100294#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
295#else
296#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
297#endif
298#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
299#define CFG_MAXARGS 16 /* max number of command args */
300#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
301
302#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
303#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
304
305#define CFG_LOAD_ADDR 0x08000000 /* default load address */
306
307#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
308
309#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
310#define CONFIG_LOOPW 1 /* enable loopw command */
311#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
312#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
313#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
314
315/*-----------------------------------------------------------------------
316 * Marvell MV64460 config settings
317 *----------------------------------------------------------------------*/
318/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
319#if defined (CONFIG_P3M750)
320#define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
321#elif defined (CONFIG_P3M7448)
322#define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
323#endif
324
325/*
326 * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
327 * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
328 * MPP[2] NC
329 * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
330 * MPP[4] PCI Monarch# GPIO IN Connected to P12
331 * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
332 * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
333 * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
334 * MPP[8] Reserved Do not use
335 * MPP[9] Reserved Do not use
336 * MPP[10] Reserved Do not use
337 * MPP[11] Reserved Do not use
338 * MPP[12] Phy 0 Interrupt Int IN
339 * MPP[13] Phy 1 Interrupt Int IN
340 * MPP[14] NC
341 * MPP[15] NC
342 * MPP[16] PCI Interrupt C Int IN Connected to P11
343 * MPP[17] PCI Interrupt D Int IN Connected to P11
344 * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
345 * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
346 * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
347 * MPP[21] NC
348 * MPP[22] GP LED Green GPIO OUT
349 * MPP[23] GP LED Red GPIO OUT
350 * MPP[24] Watchdog NMI# Int OUT
351 * MPP[25] NC
352 * MPP[26] NC
353 * MPP[27] PCI Interrupt A Int IN Connected to P11
354 * MPP[28] NC
355 * MPP[29] PCI Interrupt B Int IN Connected to P11
356 * MPP[30] Module reset GPIO OUT Board reset
357 * MPP[31] PCI EReady GPIO IN Connected to P12
358 */
359#define CFG_MPP_CONTROL_0 0x00303022
360#define CFG_MPP_CONTROL_1 0x00000000
361#define CFG_MPP_CONTROL_2 0x00004000
362#define CFG_MPP_CONTROL_3 0x00000004
363#define CFG_GPP_LEVEL_CONTROL 0x280730D0
364
365/*----------------------------------------------------------------------
366 * Initial BAT mappings
367 */
368
369/* NOTES:
370 * 1) GUARDED and WRITE_THRU not allowed in IBATS
371 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
372 */
373/* SDRAM */
374#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
375#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
376#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
377#define CFG_DBAT0U CFG_IBAT0U
378
379/* init ram */
380#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
381#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
382#define CFG_DBAT1L CFG_IBAT1L
383#define CFG_DBAT1U CFG_IBAT1U
384
385/* PCI0, PCI1 in one BAT */
386#define CFG_IBAT2L BATL_NO_ACCESS
387#define CFG_IBAT2U CFG_DBAT2U
388#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
389#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
390
391/* GT regs, bootrom, all the devices, PCI I/O */
392#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
393#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
394#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
395#define CFG_DBAT3U CFG_IBAT3U
396
397#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
398#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
399#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
400#define CFG_DBAT4U CFG_IBAT4U
401
402/* set rest out of range for Linux !!!!!!!!!!! */
403
404/* IBAT5 and DBAT5 */
405#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
406#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
407#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
408#define CFG_DBAT5U CFG_IBAT5U
409
410/* IBAT6 and DBAT6 */
411#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
412#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
413#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
414#define CFG_DBAT6U CFG_IBAT6U
415
416/* IBAT7 and DBAT7 */
417#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
418#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
419#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
420#define CFG_DBAT7U CFG_IBAT7U
421
422/*
423 * For booting Linux, the board info and command line data
424 * have to be in the first 8 MB of memory, since this is
425 * the maximum mapped by the Linux kernel during initialization.
426 */
427#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
428#define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
429
430/*-----------------------------------------------------------------------
431 * Cache Configuration
432 */
433#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger26a34562007-07-04 22:33:17 -0500434#if defined(CONFIG_CMD_KGDB)
Stefan Roese1eac2a72006-11-29 15:42:37 +0100435#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
436#endif
437
438/*-----------------------------------------------------------------------
439 * L2CR setup -- make sure this is right for your board!
440 * look in include/mpc74xx.h for the defines used here
441 */
442#define CFG_L2
443
444#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
445#define L2_INIT 0
446#else
447#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
448 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
449#endif
450
451#define L2_ENABLE (L2_INIT | L2CR_L2E)
452
453/*
454 * Internal Definitions
455 *
456 * Boot Flags
457 */
458#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
459#define BOOTFLAG_WARM 0x02 /* Software reboot */
460
461#endif /* __CONFIG_H */