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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ab1c482440ef33f34d7a4d7a14fe5e99a3704e42 / . / arch / arm / mach-omap2 / lowlevel_init.S
blob: 1a55295f9de4e02424c9b05588b180f6cb375f43 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Minkyu Kang6b96a202009-07-20 11:40:01 +0900[diff] [blame]2/*
Steve Sakomand34efc72010-06-08 13:07:46 -0700[diff] [blame]3 * Board specific setup info
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
Minkyu Kang6b96a202009-07-20 11:40:01 +0900[diff] [blame]10 */
11
Tom Rini98f92002013-03-14 11:15:25 +0000[diff] [blame]12#include <config.h>
Sricharan508a58f2011-11-15 09:49:55 -0500[diff] [blame]13#include <asm/arch/omap.h>
SRICHARAN R4a0eb752013-04-24 00:41:24 +0000[diff] [blame]14#include <asm/omap_common.h>
Joel A Fernandes90207b62012-09-18 04:30:51 +0000[diff] [blame]15#include <asm/arch/spl.h>
Aneesh V74236ac2012-03-08 07:20:18 +0000[diff] [blame]16#include <linux/linkage.h>
Sricharan78f455c2011-11-15 09:50:03 -0500[diff] [blame]17
Daniel Allred51d06382016-06-27 09:19:17 -0500[diff] [blame]18.arch_extension sec
19
Paul Kocialkowski60c7c302015-07-15 16:02:19 +0200[diff] [blame]20#ifdef CONFIG_SPL
Aneesh V74236ac2012-03-08 07:20:18 +0000[diff] [blame]21ENTRY(save_boot_params)
SRICHARAN R4a0eb752013-04-24 00:41:24 +0000[diff] [blame]22 ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
Sricharan78f455c2011-11-15 09:50:03 -0500[diff] [blame]23 str r0, [r1]
Simon Glasse11c6c22015-02-07 10:47:28 -0700[diff] [blame]24 b save_boot_params_ret
Aneesh V74236ac2012-03-08 07:20:18 +0000[diff] [blame]25ENDPROC(save_boot_params)
Keerthy1dbc40e2016-09-14 10:43:33 +0530[diff] [blame]26
27#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
28ENTRY(switch_to_hypervisor)
29
30/*
31 * Switch to hypervisor mode
32 */
33 adr r0, save_sp
34 str sp, [r0]
35 adr r1, restore_from_hyp
36 ldr r0, =0x102
37 b omap_smc1
38restore_from_hyp:
39 adr r0, save_sp
40 ldr sp, [r0]
41 MRC p15, 4, R0, c1, c0, 0
42 ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
43 orr r0, r0, r1
44 MCR p15, 4, R0, c1, c0, 0
45 b switch_to_hypervisor_ret
46save_sp:
47 .word 0x0
48ENDPROC(switch_to_hypervisor)
49#endif
Nishanth Menon49ec9492015-03-09 17:12:05 -0500[diff] [blame]50#endif
Sricharan78f455c2011-11-15 09:50:03 -0500[diff] [blame]51
Nishanth Menon6d8abe62015-03-09 17:12:03 -0500[diff] [blame]52ENTRY(omap_smc1)
Daniel Allred51d06382016-06-27 09:19:17 -0500[diff] [blame]53 push {r4-r12, lr} @ save registers - ROM code may pollute
Aneesh V8b457fa2011-06-16 23:30:52 +0000[diff] [blame]54 @ our registers
Daniel Allred51d06382016-06-27 09:19:17 -0500[diff] [blame]55 mov r12, r0 @ Service
56 mov r0, r1 @ Argument
Nishanth Menon6d8abe62015-03-09 17:12:03 -0500[diff] [blame]57
Daniel Allred51d06382016-06-27 09:19:17 -0500[diff] [blame]58 dsb
59 dmb
60 smc 0 @ SMC #0 to enter monitor mode
61 @ call ROM Code API for the service requested
62 pop {r4-r12, pc}
Nishanth Menon6d8abe62015-03-09 17:12:03 -0500[diff] [blame]63ENDPROC(omap_smc1)
Daniel Allred51d06382016-06-27 09:19:17 -0500[diff] [blame]64
65ENTRY(omap_smc_sec)
66 push {r4-r12, lr} @ save registers - ROM code may pollute
67 @ our registers
68 mov r6, #0xFF @ Indicate new Task call
69 mov r12, #0x00 @ Secure Service ID in R12
70
71 dsb
72 dmb
73 smc 0 @ SMC #0 to enter monitor mode
74
75 b omap_smc_sec_end @ exit at end of the service execution
76 nop
77
78 @ In case of IRQ happening in Secure, then ARM will branch here.
79 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
80 @ IRQ handler
81 mov r12, #0xFE
82
83 dsb
84 dmb
85 smc 0 @ SMC #0 to enter monitor mode
86
87omap_smc_sec_end:
88 pop {r4-r12, pc}
89ENDPROC(omap_smc_sec)