blob: 2f89b8c967e8e261d7fe7c4a3e70b7de876e2069 [file] [log] [blame]
Harald Welte16158772007-12-19 15:10:52 +01001/*
2 * (C) Copyright 2006 OpenMoko, Inc.
3 * Author: Harald Welte <laforge@openmoko.org>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22
Harald Welte16158772007-12-19 15:10:52 +010023#include <nand.h>
kevin.morfitt@fearnside-systems.co.uk492fb1f2009-11-03 18:08:41 +090024#include <asm/arch/s3c2410.h>
Scott Wood1a23a192008-08-13 17:04:30 -050025#include <asm/io.h>
Harald Welte16158772007-12-19 15:10:52 +010026
Harald Welte16158772007-12-19 15:10:52 +010027#define S3C2410_NFCONF_EN (1<<15)
28#define S3C2410_NFCONF_512BYTE (1<<14)
29#define S3C2410_NFCONF_4STEP (1<<13)
30#define S3C2410_NFCONF_INITECC (1<<12)
31#define S3C2410_NFCONF_nFCE (1<<11)
32#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
33#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
34#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
35
Scott Wood1a23a192008-08-13 17:04:30 -050036#define S3C2410_ADDR_NALE 4
37#define S3C2410_ADDR_NCLE 8
38
Hui.Tang5e1ded52009-11-18 16:24:04 +080039#ifdef CONFIG_NAND_SPL
40
41/* in the early stage of NAND flash booting, printf() is not available */
42#define printf(fmt, args...)
43
44static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
45{
46 int i;
47 struct nand_chip *this = mtd->priv;
48
49 for (i = 0; i < len; i++)
50 buf[i] = readb(this->IO_ADDR_R);
51}
52#endif
53
Scott Wood1a23a192008-08-13 17:04:30 -050054static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Harald Welte16158772007-12-19 15:10:52 +010055{
56 struct nand_chip *chip = mtd->priv;
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090057 struct s3c2410_nand *nand = s3c2410_get_base_nand();
Harald Welte16158772007-12-19 15:10:52 +010058
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090059 debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
Harald Welte16158772007-12-19 15:10:52 +010060
Scott Wood1a23a192008-08-13 17:04:30 -050061 if (ctrl & NAND_CTRL_CHANGE) {
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090062 ulong IO_ADDR_W = (ulong)nand;
Scott Wood1a23a192008-08-13 17:04:30 -050063
64 if (!(ctrl & NAND_CLE))
65 IO_ADDR_W |= S3C2410_ADDR_NCLE;
66 if (!(ctrl & NAND_ALE))
67 IO_ADDR_W |= S3C2410_ADDR_NALE;
68
69 chip->IO_ADDR_W = (void *)IO_ADDR_W;
70
71 if (ctrl & NAND_NCE)
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090072 writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
73 &nand->NFCONF);
Scott Wood1a23a192008-08-13 17:04:30 -050074 else
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090075 writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
76 &nand->NFCONF);
Harald Welte16158772007-12-19 15:10:52 +010077 }
Scott Wood1a23a192008-08-13 17:04:30 -050078
79 if (cmd != NAND_CMD_NONE)
80 writeb(cmd, chip->IO_ADDR_W);
Harald Welte16158772007-12-19 15:10:52 +010081}
82
83static int s3c2410_dev_ready(struct mtd_info *mtd)
84{
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090085 struct s3c2410_nand *nand = s3c2410_get_base_nand();
86 debugX(1, "dev_ready\n");
87 return readl(&nand->NFSTAT) & 0x01;
Harald Welte16158772007-12-19 15:10:52 +010088}
89
90#ifdef CONFIG_S3C2410_NAND_HWECC
91void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
92{
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +090093 struct s3c2410_nand *nand = s3c2410_get_base_nand();
94 debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
95 writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
Harald Welte16158772007-12-19 15:10:52 +010096}
97
98static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
99 u_char *ecc_code)
100{
Hui.Tang5e1ded52009-11-18 16:24:04 +0800101 struct s3c2410_nand *nand = s3c2410_get_base_nand();
102 ecc_code[0] = readb(&nand->NFECC);
103 ecc_code[1] = readb(&nand->NFECC + 1);
104 ecc_code[2] = readb(&nand->NFECC + 2);
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900105 debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
106 mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
Harald Welte16158772007-12-19 15:10:52 +0100107
108 return 0;
109}
110
111static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
112 u_char *read_ecc, u_char *calc_ecc)
113{
114 if (read_ecc[0] == calc_ecc[0] &&
115 read_ecc[1] == calc_ecc[1] &&
116 read_ecc[2] == calc_ecc[2])
117 return 0;
118
119 printf("s3c2410_nand_correct_data: not implemented\n");
120 return -1;
121}
122#endif
123
124int board_nand_init(struct nand_chip *nand)
125{
126 u_int32_t cfg;
127 u_int8_t tacls, twrph0, twrph1;
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900128 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
129 struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
Harald Welte16158772007-12-19 15:10:52 +0100130
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900131 debugX(1, "board_nand_init()\n");
Harald Welte16158772007-12-19 15:10:52 +0100132
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900133 writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
Harald Welte16158772007-12-19 15:10:52 +0100134
135 /* initialize hardware */
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900136 twrph0 = 3;
137 twrph1 = 0;
138 tacls = 0;
Harald Welte16158772007-12-19 15:10:52 +0100139
140 cfg = S3C2410_NFCONF_EN;
141 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
142 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
143 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900144 writel(cfg, &nand_reg->NFCONF);
Harald Welte16158772007-12-19 15:10:52 +0100145
146 /* initialize nand_chip data structure */
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900147 nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
Harald Welte16158772007-12-19 15:10:52 +0100148
Hui.Tang5e1ded52009-11-18 16:24:04 +0800149 nand->select_chip = NULL;
150
Harald Welte16158772007-12-19 15:10:52 +0100151 /* read_buf and write_buf are default */
152 /* read_byte and write_byte are default */
Hui.Tang5e1ded52009-11-18 16:24:04 +0800153#ifdef CONFIG_NAND_SPL
154 nand->read_buf = nand_read_buf;
155#endif
Harald Welte16158772007-12-19 15:10:52 +0100156
157 /* hwcontrol always must be implemented */
Scott Wood1a23a192008-08-13 17:04:30 -0500158 nand->cmd_ctrl = s3c2410_hwcontrol;
Harald Welte16158772007-12-19 15:10:52 +0100159
160 nand->dev_ready = s3c2410_dev_ready;
161
162#ifdef CONFIG_S3C2410_NAND_HWECC
Scott Wood1a23a192008-08-13 17:04:30 -0500163 nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
164 nand->ecc.calculate = s3c2410_nand_calculate_ecc;
165 nand->ecc.correct = s3c2410_nand_correct_data;
Hui.Tang5e1ded52009-11-18 16:24:04 +0800166 nand->ecc.mode = NAND_ECC_HW;
167 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
168 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
Harald Welte16158772007-12-19 15:10:52 +0100169#else
Scott Wood1a23a192008-08-13 17:04:30 -0500170 nand->ecc.mode = NAND_ECC_SOFT;
Harald Welte16158772007-12-19 15:10:52 +0100171#endif
172
173#ifdef CONFIG_S3C2410_NAND_BBT
174 nand->options = NAND_USE_FLASH_BBT;
175#else
176 nand->options = 0;
177#endif
178
kevin.morfitt@fearnside-systems.co.uk3d1988a2009-10-10 13:34:09 +0900179 debugX(1, "end of nand_init\n");
Harald Welte16158772007-12-19 15:10:52 +0100180
181 return 0;
182}