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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenka562e1b2005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenka562e1b2005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Menga1875592016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenka562e1b2005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenka562e1b2005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenka562e1b2005-01-09 18:21:42 +000029 * ---
30 */
31
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_CLK 66000000
33#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenka562e1b2005-01-09 18:21:42 +000034
TsiChungLiew67064242007-08-15 19:41:06 -050035/* Enable Dma Timer */
36#define CONFIG_MCFTMR
wdenka562e1b2005-01-09 18:21:42 +000037
38/* ---
39 * Define baudrate for UART1 (console output, tftp, ...)
40 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenka562e1b2005-01-09 18:21:42 +000042 * interface
43 * ---
44 */
45
TsiChungLiew67064242007-08-15 19:41:06 -050046#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_UART_PORT (0)
wdenka562e1b2005-01-09 18:21:42 +000048
49/* ---
50 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
51 * timeout acc. to your needs
52 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
53 * for 10 sec
54 * ---
55 */
56
57#if 0
58#define CONFIG_WATCHDOG
59#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
60#endif
61
62/* ---
63 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
64 * bootloader residing in flash ('chainloading'); if you want to use
65 * chainloading or want to compile a u-boot binary that can be loaded into
66 * RAM via BDM set
Wolfgang Denk53677ef2008-05-20 16:00:29 +020067 * "#if 0" to "#if 1"
wdenka562e1b2005-01-09 18:21:42 +000068 * You will need a first stage bootloader then, e. g. colilo or a working BDM
69 * cable (Background Debug Mode)
70 *
71 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
72 *
Wolfgang Denk14d0a022010-10-07 21:51:12 +020073 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenka562e1b2005-01-09 18:21:42 +000074 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
75 *
76 * ---
77 */
78
79#if 0
80#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
81#endif
82
83/* ---
84 * Configuration for environment
85 * Environment is embedded in u-boot in the second sector of the flash
86 * ---
87 */
88
angelo@sysam.it5296cb12015-03-29 22:54:16 +020089#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -060090 . = DEFINED(env_offset) ? env_offset : .; \
91 env/embedded.o(.text);
Jon Loeliger37e4f242007-07-04 22:31:56 -050092
93/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050094 * BOOTP options
95 */
96#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger80ff4f92007-07-10 09:29:01 -050097
Jon Loeliger80ff4f92007-07-10 09:29:01 -050098/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050099 * Command line configuration.
wdenka562e1b2005-01-09 18:21:42 +0000100 */
wdenka562e1b2005-01-09 18:21:42 +0000101
TsiChungLiew67064242007-08-15 19:41:06 -0500102#ifdef CONFIG_MCFFEC
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500103# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104# define CONFIG_SYS_DISCOVER_PHY
105# define CONFIG_SYS_RX_ETH_BUFFER 8
106# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
108# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew67064242007-08-15 19:41:06 -0500109# define FECDUPLEX FULL
110# define FECSPEED _100BASET
111# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
113# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500114# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew67064242007-08-15 19:41:06 -0500116#endif
wdenka562e1b2005-01-09 18:21:42 +0000117
118/*
119 *-----------------------------------------------------------------------------
120 * Define user parameters that have to be customized most likely
121 *-----------------------------------------------------------------------------
122 */
123
124/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
125
wdenka562e1b2005-01-09 18:21:42 +0000126/* The following settings will be contained in the environment block ; if you
127want to use a neutral environment all those settings can be manually set in
128u-boot: 'set' command */
129
130#if 0
131
132#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
133enter a valid image address in flash */
134
wdenka562e1b2005-01-09 18:21:42 +0000135/* User network settings */
136
wdenka562e1b2005-01-09 18:21:42 +0000137#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
138#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
139
140#endif
141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
wdenka562e1b2005-01-09 18:21:42 +0000143from which user programs will be started */
144
145/*---*/
146
wdenka562e1b2005-01-09 18:21:42 +0000147/*
148 *-----------------------------------------------------------------------------
149 * End of user parameters to be customized
150 *-----------------------------------------------------------------------------
151 */
152
153/* ---
154 * Defines memory range for test
155 * ---
156 */
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MEMTEST_START 0x400
159#define CONFIG_SYS_MEMTEST_END 0x380000
wdenka562e1b2005-01-09 18:21:42 +0000160
161/* ---
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 * ---
166 */
167
168/* ---
169 * Base register address
170 * ---
171 */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenka562e1b2005-01-09 18:21:42 +0000174
175/* ---
176 * System Conf. Reg. & System Protection Reg.
177 * ---
178 */
179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_SCR 0x0003
181#define CONFIG_SYS_SPR 0xffff
wdenka562e1b2005-01-09 18:21:42 +0000182
183/* ---
184 * Ethernet settings
185 * ---
186 */
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_DISCOVER_PHY
189#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenka562e1b2005-01-09 18:21:42 +0000190
191/*-----------------------------------------------------------------------
192 * Definitions for initial stack pointer and data area (in internal SRAM)
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200195#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200196#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka562e1b2005-01-09 18:21:42 +0000198
199/*-----------------------------------------------------------------------
200 * Start addresses for the final memory configuration
201 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenka562e1b2005-01-09 18:21:42 +0000203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenka562e1b2005-01-09 18:21:42 +0000205
206/*
207 *-------------------------------------------------------------------------
208 * RAM SIZE (is defined above)
209 *-----------------------------------------------------------------------
210 */
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenka562e1b2005-01-09 18:21:42 +0000213
214/*
215 *-----------------------------------------------------------------------
216 */
217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenka562e1b2005-01-09 18:21:42 +0000219
220#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenka562e1b2005-01-09 18:21:42 +0000222#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenka562e1b2005-01-09 18:21:42 +0000224#endif
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_MONITOR_LEN 0x20000
227#define CONFIG_SYS_MALLOC_LEN (256 << 10)
228#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenka562e1b2005-01-09 18:21:42 +0000229
230/*
231 * For booting Linux, the board info and command line data
232 * have to be in the first 8 MB of memory, since this is
233 * the maximum mapped by the Linux kernel during initialization ??
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka562e1b2005-01-09 18:21:42 +0000236
237/*-----------------------------------------------------------------------
238 * FLASH organization
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
242#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenka562e1b2005-01-09 18:21:42 +0000243
244/*-----------------------------------------------------------------------
245 * Cache Configuration
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_CACHELINE_SIZE 16
wdenka562e1b2005-01-09 18:21:42 +0000248
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600249#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200250 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600251#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200252 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600253#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
254#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
255 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
256 CF_ACR_EN | CF_ACR_SM_ALL)
257#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
258 CF_CACR_DISD | CF_CACR_INVI | \
259 CF_CACR_CEIB | CF_CACR_DCM | \
260 CF_CACR_EUSP)
261
wdenka562e1b2005-01-09 18:21:42 +0000262/*-----------------------------------------------------------------------
263 * Memory bank definitions
264 *
265 * Please refer also to Motorola Coldfire user manual - Chapter XXX
266 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
269#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
wdenka562e1b2005-01-09 18:21:42 +0000270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_BR1_PRELIM 0
272#define CONFIG_SYS_OR1_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_BR2_PRELIM 0
275#define CONFIG_SYS_OR2_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_BR3_PRELIM 0
278#define CONFIG_SYS_OR3_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_BR4_PRELIM 0
281#define CONFIG_SYS_OR4_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_BR5_PRELIM 0
284#define CONFIG_SYS_OR5_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_BR6_PRELIM 0
287#define CONFIG_SYS_OR6_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_BR7_PRELIM 0x00000701
290#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
wdenka562e1b2005-01-09 18:21:42 +0000291
292/*-----------------------------------------------------------------------
293 * LED config
294 */
295#define LED_STAT_0 0xffff /*all LEDs off*/
296#define LED_STAT_1 0xfffe
297#define LED_STAT_2 0xfffd
298#define LED_STAT_3 0xfffb
299#define LED_STAT_4 0xfff7
300#define LED_STAT_5 0xffef
301#define LED_STAT_6 0xffdf
302#define LED_STAT_7 0xff00 /*all LEDs on*/
303
304/*-----------------------------------------------------------------------
305 * Port configuration (GPIO)
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenka562e1b2005-01-09 18:21:42 +0000308GPIO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenka562e1b2005-01-09 18:21:42 +0000310(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
312#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenka562e1b2005-01-09 18:21:42 +0000313configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
315#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
316#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenka562e1b2005-01-09 18:21:42 +0000317
318#endif /* _CONFIG_COBRA5272_H */