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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard0c563102017-02-21 13:37:10 +01002/*
3 * Pinctrl driver for STMicroelectronics STi SoCs
4 *
Patrice Chotardfb48bc42017-10-23 09:53:57 +02005 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotard0c563102017-02-21 13:37:10 +01007 */
8
9#include <common.h>
10#include <bitfield.h>
11#include <dm.h>
12#include <errno.h>
13#include <regmap.h>
14#include <syscon.h>
15#include <asm/io.h>
16#include <dm/pinctrl.h>
Simon Glasseb41d8a2020-05-10 11:40:08 -060017#include <linux/bug.h>
Simon Glass4d72caa2020-05-10 11:40:01 -060018#include <linux/libfdt.h>
Patrice Chotard0c563102017-02-21 13:37:10 +010019
20DECLARE_GLOBAL_DATA_PTR;
21
22#define MAX_STI_PINCONF_ENTRIES 7
23/* Output enable */
24#define OE (1 << 27)
25/* Pull Up */
26#define PU (1 << 26)
27/* Open Drain */
28#define OD (1 << 25)
29
30/* User-frendly defines for Pin Direction */
31 /* oe = 0, pu = 0, od = 0 */
32#define IN (0)
33 /* oe = 0, pu = 1, od = 0 */
34#define IN_PU (PU)
35 /* oe = 1, pu = 0, od = 0 */
36#define OUT (OE)
37 /* oe = 1, pu = 1, od = 0 */
38#define OUT_PU (OE | PU)
39 /* oe = 1, pu = 0, od = 1 */
40#define BIDIR (OE | OD)
41 /* oe = 1, pu = 1, od = 1 */
42#define BIDIR_PU (OE | PU | OD)
43
44struct sti_pinctrl_platdata {
45 struct regmap *regmap;
46};
47
48struct sti_pin_desc {
49 unsigned char bank;
50 unsigned char pin;
51 unsigned char alt;
52 int dir;
53};
54
55/*
56 * PIO alternative Function selector
57 */
58void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
59{
60 struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
61 unsigned long sysconf, *sysconfreg;
62 int alt = pin_desc->alt;
63 int bank = pin_desc->bank;
64 int pin = pin_desc->pin;
65
Masahiro Yamada8c1de5e2018-04-19 12:14:01 +090066 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start;
Patrice Chotard0c563102017-02-21 13:37:10 +010067
68 switch (bank) {
69 case 0 ... 5: /* in "SBC Bank" */
70 sysconfreg += bank;
71 break;
72 case 10 ... 20: /* in "FRONT Bank" */
73 sysconfreg += bank - 10;
74 break;
75 case 30 ... 35: /* in "REAR Bank" */
76 sysconfreg += bank - 30;
77 break;
78 case 40 ... 42: /* in "FLASH Bank" */
79 sysconfreg += bank - 40;
80 break;
81 default:
82 BUG();
83 return;
84 }
85
86 sysconf = readl(sysconfreg);
87 sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
88 writel(sysconf, sysconfreg);
89}
90
91/* pin configuration */
92void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
93{
94 struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
95 int bit;
96 int oe = 0, pu = 0, od = 0;
97 unsigned long *sysconfreg;
98 int bank = pin_desc->bank;
99
Masahiro Yamada8c1de5e2018-04-19 12:14:01 +0900100 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start + 40;
Patrice Chotard0c563102017-02-21 13:37:10 +0100101
102 /*
103 * NOTE: The PIO configuration for the PIO pins in the
104 * "FLASH Bank" are different from all the other banks!
105 * Specifically, the output-enable pin control register
106 * (SYS_CFG_3040) and the pull-up pin control register
107 * (SYS_CFG_3050), are both classed as being "reserved".
108 * Hence, we do not write to these registers to configure
109 * the OE and PU features for PIOs in this bank. However,
110 * the open-drain pin control register (SYS_CFG_3060)
111 * follows the style of the other banks, and so we can
112 * treat that register normally.
113 *
114 * Being pedantic, we should configure the PU and PD features
115 * in the "FLASH Bank" explicitly instead using the four
116 * SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
117 * would necessitate passing in the alternate function number
118 * to this function, and adding some horrible complexity here.
119 * Alternatively, we could just perform 4 32-bit "pokes" to
120 * these four SYS_CFG registers early in the initialization.
121 * In practice, these four SYS_CFG registers are correct
122 * after a reset, and U-Boot does not need to change them, so
123 * we (cheat and) rely on these registers being correct.
124 * WARNING: Please be aware of this (pragmatic) behaviour!
125 */
126 int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
127
128 switch (pin_desc->dir) {
129 case IN:
130 oe = 0; pu = 0; od = 0;
131 break;
132 case IN_PU:
133 oe = 0; pu = 1; od = 0;
134 break;
135 case OUT:
136 oe = 1; pu = 0; od = 0;
137 break;
138 case BIDIR:
139 oe = 1; pu = 0; od = 1;
140 break;
141 case BIDIR_PU:
142 oe = 1; pu = 1; od = 1;
143 break;
144
145 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900146 pr_err("%s invalid direction value: 0x%x\n",
Patrice Chotard0c563102017-02-21 13:37:10 +0100147 __func__, pin_desc->dir);
148 BUG();
149 break;
150 }
151
152 switch (bank) {
153 case 0 ... 5: /* in "SBC Bank" */
154 sysconfreg += bank / 4;
155 break;
156 case 10 ... 20: /* in "FRONT Bank" */
157 bank -= 10;
158 sysconfreg += bank / 4;
159 break;
160 case 30 ... 35: /* in "REAR Bank" */
161 bank -= 30;
162 sysconfreg += bank / 4;
163 break;
164 case 40 ... 42: /* in "FLASH Bank" */
165 bank -= 40;
166 sysconfreg += bank / 4;
167 flashss = 1; /* pin is in the Flash Sub-System */
168 break;
169 default:
170 BUG();
171 return;
172 }
173
174 bit = ((bank * 8) + pin_desc->pin) % 32;
175
176 /*
177 * set the "Output Enable" pin control
178 * but, do nothing if in the flashSS
179 */
180 if (!flashss) {
181 if (oe)
182 generic_set_bit(bit, sysconfreg);
183 else
184 generic_clear_bit(bit, sysconfreg);
185 }
186
187 sysconfreg += 10; /* skip to next set of syscfg registers */
188
189 /*
190 * set the "Pull Up" pin control
191 * but, do nothing if in the FlashSS
192 */
193
194 if (!flashss) {
195 if (pu)
196 generic_set_bit(bit, sysconfreg);
197 else
198 generic_clear_bit(bit, sysconfreg);
199 }
200
201 sysconfreg += 10; /* skip to next set of syscfg registers */
202
203 /* set the "Open Drain Enable" pin control */
204 if (od)
205 generic_set_bit(bit, sysconfreg);
206 else
207 generic_clear_bit(bit, sysconfreg);
208}
209
210
211static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
212{
213 struct fdtdec_phandle_args args;
214 const void *blob = gd->fdt_blob;
215 const char *prop_name;
216 int node = dev_of_offset(config);
217 int property_offset, prop_len;
218 int pinconf_node, ret, count;
219 const char *bank_name;
220 u32 cells[MAX_STI_PINCONF_ENTRIES];
221
222 struct sti_pin_desc pin_desc;
223
224 /* go to next node "st,pins" which contains the pins configuration */
225 pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
226
227 /*
228 * parse each pins configuration which looks like :
229 * pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
230 */
231
232 fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
233 fdt_getprop_by_offset(blob, property_offset, &prop_name,
234 &prop_len);
235
236 /* extract the bank of the pin description */
237 ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
238 prop_name, "#gpio-cells",
239 0, 0, &args);
240 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900241 pr_err("Can't get the gpio bank phandle: %d\n", ret);
Patrice Chotard0c563102017-02-21 13:37:10 +0100242 return ret;
243 }
244
245 bank_name = fdt_getprop(blob, args.node, "st,bank-name",
246 &count);
247 if (count < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900248 pr_err("Can't find bank-name property %d\n", count);
Patrice Chotard0c563102017-02-21 13:37:10 +0100249 return -EINVAL;
250 }
251
252 pin_desc.bank = trailing_strtoln(bank_name, NULL);
253
254 count = fdtdec_get_int_array_count(blob, pinconf_node,
255 prop_name, cells,
256 ARRAY_SIZE(cells));
257 if (count < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900258 pr_err("Bad pin configuration array %d\n", count);
Patrice Chotard0c563102017-02-21 13:37:10 +0100259 return -EINVAL;
260 }
261
262 if (count > MAX_STI_PINCONF_ENTRIES) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900263 pr_err("Unsupported pinconf array count %d\n", count);
Patrice Chotard0c563102017-02-21 13:37:10 +0100264 return -EINVAL;
265 }
266
267 pin_desc.pin = cells[1];
268 pin_desc.alt = cells[2];
269 pin_desc.dir = cells[3];
270
271 sti_alternate_select(dev, &pin_desc);
272 sti_pin_configure(dev, &pin_desc);
273 };
274
275 return 0;
276}
277
278static int sti_pinctrl_probe(struct udevice *dev)
279{
280 struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
281 struct udevice *syscon;
282 int err;
283
284 /* get corresponding syscon phandle */
285 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
286 "st,syscfg", &syscon);
287 if (err) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900288 pr_err("unable to find syscon device\n");
Patrice Chotard0c563102017-02-21 13:37:10 +0100289 return err;
290 }
291
292 plat->regmap = syscon_get_regmap(syscon);
293 if (!plat->regmap) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900294 pr_err("unable to find regmap\n");
Patrice Chotard0c563102017-02-21 13:37:10 +0100295 return -ENODEV;
296 }
297
298 return 0;
299}
300
301static const struct udevice_id sti_pinctrl_ids[] = {
302 { .compatible = "st,stih407-sbc-pinctrl" },
303 { .compatible = "st,stih407-front-pinctrl" },
304 { .compatible = "st,stih407-rear-pinctrl" },
305 { .compatible = "st,stih407-flash-pinctrl" },
306 { }
307};
308
309const struct pinctrl_ops sti_pinctrl_ops = {
310 .set_state = sti_pinctrl_set_state,
311};
312
313U_BOOT_DRIVER(pinctrl_sti) = {
314 .name = "pinctrl_sti",
315 .id = UCLASS_PINCTRL,
316 .of_match = sti_pinctrl_ids,
317 .ops = &sti_pinctrl_ops,
318 .probe = sti_pinctrl_probe,
319 .platdata_auto_alloc_size = sizeof(struct sti_pinctrl_platdata),
320 .ops = &sti_pinctrl_ops,
321};