| Shengzhou Liu | ae6b03f | 2011-11-22 16:51:13 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor |
| 3 | * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the Free |
| 7 | * Software Foundation; either version 2 of the License, or (at your option) |
| 8 | * any later version. |
| 9 | * |
| 10 | * This file provides support for the QIXIS of some Freescale reference boards. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __QIXIS_H_ |
| 14 | #define __QIXIS_H_ |
| 15 | |
| 16 | struct qixis { |
| 17 | u8 id; /* ID value uniquely identifying each QDS board type */ |
| 18 | u8 arch; /* Board version information */ |
| 19 | u8 scver; /* QIXIS Version Register */ |
| 20 | u8 model; /* Information of software programming model version */ |
| 21 | u8 tagdata; |
| 22 | u8 ctl_sys; |
| 23 | u8 aux; /* Auxiliary Register,0x06 */ |
| 24 | u8 clk_spd; |
| 25 | u8 stat_dut; |
| 26 | u8 stat_sys; |
| 27 | u8 stat_alrm; |
| 28 | u8 present; |
| 29 | u8 ctl_sys2; |
| 30 | u8 rcw_ctl; |
| 31 | u8 ctl_led; |
| 32 | u8 i2cblk; |
| 33 | u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ |
| 34 | u8 rcfg_st; |
| 35 | u8 dcm_ad; |
| 36 | u8 dcm_da; |
| 37 | u8 dcmd; |
| 38 | u8 dmsg; |
| 39 | u8 gdc; |
| 40 | u8 gdd; /* DCM Debug Data Register,0x17 */ |
| 41 | u8 dmack; |
| 42 | u8 res1[6]; |
| 43 | u8 watch; /* Watchdog Register,0x1F */ |
| 44 | u8 pwr_ctl[2]; /* Power Control Register,0x20 */ |
| 45 | u8 res2[2]; |
| 46 | u8 pwr_stat[4]; /* Power Status Register,0x24 */ |
| 47 | u8 res3[8]; |
| 48 | u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ |
| 49 | u8 res4[2]; |
| 50 | u8 sclk[3]; /* Clock Configuration Registers,0x34 */ |
| 51 | u8 res5; |
| 52 | u8 dclk[3]; |
| 53 | u8 res6; |
| 54 | u8 clk_dspd[3]; |
| 55 | u8 res7; |
| 56 | u8 rst_ctl; /* Reset Control Register,0x40 */ |
| 57 | u8 rst_stat; /* Reset Status Register */ |
| 58 | u8 rst_rsn; /* Reset Reason Register */ |
| 59 | u8 rst_frc[2]; /* Reset Force Registers,0x43 */ |
| 60 | u8 res8[11]; |
| 61 | u8 brdcfg[16]; /* Board Configuration Register,0x50 */ |
| 62 | u8 dutcfg[16]; |
| 63 | u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ |
| 64 | u8 rcw_data; |
| 65 | u8 res9[5]; |
| 66 | u8 post_ctl; |
| 67 | u8 post_stat; |
| 68 | u8 post_dat[2]; |
| 69 | u8 pi_d[4]; |
| 70 | u8 gpio_io[4]; |
| 71 | u8 gpio_dir[4]; |
| 72 | u8 res10[20]; |
| 73 | u8 rjtag_ctl; |
| 74 | u8 rjtag_dat; |
| 75 | u8 res11[2]; |
| 76 | u8 trig_src[4]; |
| 77 | u8 trig_dst[4]; |
| 78 | u8 trig_stat; |
| 79 | u8 res12[3]; |
| 80 | u8 trig_ctr[4]; |
| 81 | u8 res13[48]; |
| 82 | u8 aux2[4]; /* Auxiliary Registers,0xE0 */ |
| 83 | u8 res14[10]; |
| 84 | u8 aux_ad; |
| 85 | u8 aux_da; |
| 86 | u8 res15[16]; |
| 87 | }; |
| 88 | |
| 89 | #define QIXIS_BASE 0xffdf0000 |
| 90 | #define QIXIS_LBMAP_SWITCH 7 |
| 91 | #define QIXIS_LBMAP_MASK 0x0f |
| 92 | #define QIXIS_LBMAP_SHIFT 0 |
| 93 | #define QIXIS_LBMAP_ALTBANK 0x04 |
| 94 | |
| 95 | u8 qixis_read(unsigned int reg); |
| 96 | void qixis_write(unsigned int reg, u8 value); |
| 97 | |
| 98 | #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) |
| 99 | #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) |
| 100 | |
| 101 | #endif |