Trevor Woerner | 18138ab | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 1 | if ARCH_TEGRA |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 2 | |
Simon Glass | 83061db | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 3 | config SPL_GPIO |
Simon Glass | 53b5bf3 | 2016-09-12 23:18:39 -0600 | [diff] [blame] | 4 | default y |
| 5 | |
Simon Glass | 77d2f7f | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 6 | config SPL_LIBCOMMON_SUPPORT |
| 7 | default y |
| 8 | |
Simon Glass | cc4288e | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y |
| 11 | |
Simon Glass | 2a73606 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 12 | config SPL_SERIAL |
Simon Glass | e00f76c | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 13 | default y |
| 14 | |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 15 | config TEGRA_CLKRST |
| 16 | bool |
| 17 | |
Svyatoslav Ryhel | 8ed2bd1 | 2023-02-14 19:35:35 +0200 | [diff] [blame] | 18 | config TEGRA_CRYPTO |
| 19 | bool "Tegra AES128 crypto module" |
| 20 | select AES |
Svyatoslav Ryhel | 8ed2bd1 | 2023-02-14 19:35:35 +0200 | [diff] [blame] | 21 | |
Thierry Reding | 9e57819 | 2019-04-15 11:32:19 +0200 | [diff] [blame] | 22 | config TEGRA_GP_PADCTRL |
| 23 | bool |
| 24 | |
Stephen Warren | 49626ea | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 25 | config TEGRA_IVC |
| 26 | bool "Tegra IVC protocol" |
| 27 | help |
| 28 | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC |
| 29 | (Inter Processor Communication) framework. Within the context of |
| 30 | U-Boot, it is typically used for communication between the main CPU |
| 31 | and various auxiliary processors. |
| 32 | |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 33 | config TEGRA_MC |
| 34 | bool |
| 35 | |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 36 | config TEGRA_PINCTRL |
| 37 | bool |
| 38 | |
Thierry Reding | e19143b | 2019-04-15 11:32:22 +0200 | [diff] [blame] | 39 | config TEGRA_PMC |
| 40 | bool |
| 41 | |
Thierry Reding | f9ec2ec | 2019-04-15 11:32:25 +0200 | [diff] [blame] | 42 | config TEGRA_PMC_SECURE |
| 43 | bool |
| 44 | depends on TEGRA_PMC |
| 45 | |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 46 | config TEGRA_COMMON |
| 47 | bool "Tegra common options" |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 48 | select BOARD_EARLY_INIT_F |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 49 | select CLK |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 50 | select DM |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 51 | select DM_GPIO |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 52 | select DM_I2C |
Simon Glass | f77f5e9 | 2015-10-18 21:17:16 -0600 | [diff] [blame] | 53 | select DM_KEYBOARD |
Tom Warren | 6a474db | 2016-09-13 10:45:48 -0600 | [diff] [blame] | 54 | select DM_MMC |
Simon Glass | 91c08af | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 55 | select DM_PWM |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 56 | select DM_RESET |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 57 | select DM_SERIAL |
| 58 | select DM_SPI |
| 59 | select DM_SPI_FLASH |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 60 | select MISC |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 61 | select OF_CONTROL |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 62 | select SPI |
Michal Simek | 08a00cb | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 63 | imply CMD_DM |
Daniel Thompson | 221a949 | 2017-05-19 17:26:58 +0100 | [diff] [blame] | 64 | imply CRC32_VERIFY |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 65 | |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 66 | config TEGRA_NO_BPMP |
| 67 | bool "Tegra common options for SoCs without BPMP" |
| 68 | select TEGRA_CAR |
| 69 | select TEGRA_CAR_CLOCK |
| 70 | select TEGRA_CAR_RESET |
| 71 | |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 72 | config TEGRA_ARMV7_COMMON |
| 73 | bool "Tegra 32-bit common options" |
Simon Glass | 3077026 | 2020-07-19 13:56:00 -0600 | [diff] [blame] | 74 | select BINMAN |
Lokesh Vutla | acf1500 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 75 | select CPU_V7A |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 76 | select SPL |
Ley Foon Tan | 0680f1b | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 77 | select SPL_BOARD_INIT if SPL |
Tom Rini | a2ac2b9 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 78 | select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 79 | select SUPPORT_SPL |
Svyatoslav Ryhel | 412a4c6 | 2023-02-01 10:53:03 +0200 | [diff] [blame] | 80 | select TIMER |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 81 | select TEGRA_CLKRST |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 82 | select TEGRA_COMMON |
Stephen Warren | 601800b | 2016-05-12 12:07:41 -0600 | [diff] [blame] | 83 | select TEGRA_GPIO |
Thierry Reding | 9e57819 | 2019-04-15 11:32:19 +0200 | [diff] [blame] | 84 | select TEGRA_GP_PADCTRL |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 85 | select TEGRA_MC |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 86 | select TEGRA_NO_BPMP |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 87 | select TEGRA_PINCTRL |
Thierry Reding | e19143b | 2019-04-15 11:32:22 +0200 | [diff] [blame] | 88 | select TEGRA_PMC |
Svyatoslav Ryhel | 412a4c6 | 2023-02-01 10:53:03 +0200 | [diff] [blame] | 89 | select TEGRA_TIMER |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 90 | |
| 91 | config TEGRA_ARMV8_COMMON |
| 92 | bool "Tegra 64-bit common options" |
| 93 | select ARM64 |
Masahiro Yamada | 382de4a | 2019-06-26 13:51:46 +0900 | [diff] [blame] | 94 | select INIT_SP_RELATIVE |
Stephen Warren | ddecaaf | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 95 | select LINUX_KERNEL_IMAGE_HEADER |
Thierry Reding | 74a50ac | 2019-04-15 11:32:32 +0200 | [diff] [blame] | 96 | select POSITION_INDEPENDENT |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 97 | select TEGRA_COMMON |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 98 | |
Stephen Warren | ddecaaf | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 99 | if TEGRA_ARMV8_COMMON |
| 100 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE |
| 101 | default 0x80000000 |
| 102 | endif |
| 103 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 104 | choice |
| 105 | prompt "Tegra SoC select" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 106 | optional |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 107 | |
| 108 | config TEGRA20 |
| 109 | bool "Tegra20 family" |
Tom Rini | 8dda2e2 | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 110 | select ARM_ERRATA_716044 |
| 111 | select ARM_ERRATA_742230 |
| 112 | select ARM_ERRATA_751472 |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 113 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 114 | |
| 115 | config TEGRA30 |
| 116 | bool "Tegra30 family" |
Tom Rini | 8dda2e2 | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 117 | select ARM_ERRATA_743622 |
| 118 | select ARM_ERRATA_751472 |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 119 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 120 | |
| 121 | config TEGRA114 |
| 122 | bool "Tegra114 family" |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 123 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 124 | |
| 125 | config TEGRA124 |
| 126 | bool "Tegra124 family" |
Tom Warren | 56079ec | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 127 | select TEGRA_ARMV7_COMMON |
Simon Glass | 66de3ee | 2017-07-25 08:29:58 -0600 | [diff] [blame] | 128 | imply REGMAP |
| 129 | imply SYSCON |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 130 | |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 131 | config TEGRA210 |
| 132 | bool "Tegra210 family" |
Tom Rini | 5afdcca | 2021-08-19 14:19:39 -0400 | [diff] [blame] | 133 | select GICV2 |
Svyatoslav Ryhel | 412a4c6 | 2023-02-01 10:53:03 +0200 | [diff] [blame] | 134 | select TIMER |
Stephen Warren | 15bcc62 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 135 | select TEGRA_ARMV8_COMMON |
Thierry Reding | b64e0b9 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 136 | select TEGRA_CLKRST |
Michal Simek | 5ed063d | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 137 | select TEGRA_GPIO |
Thierry Reding | 9e57819 | 2019-04-15 11:32:19 +0200 | [diff] [blame] | 138 | select TEGRA_GP_PADCTRL |
Thierry Reding | 1a869c7 | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 139 | select TEGRA_MC |
Stephen Warren | 140a9ea | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 140 | select TEGRA_NO_BPMP |
Thierry Reding | 07ea02b | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 141 | select TEGRA_PINCTRL |
Thierry Reding | e19143b | 2019-04-15 11:32:22 +0200 | [diff] [blame] | 142 | select TEGRA_PMC |
Thierry Reding | f9ec2ec | 2019-04-15 11:32:25 +0200 | [diff] [blame] | 143 | select TEGRA_PMC_SECURE |
Svyatoslav Ryhel | 412a4c6 | 2023-02-01 10:53:03 +0200 | [diff] [blame] | 144 | select TEGRA_TIMER |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 145 | |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 146 | config TEGRA186 |
| 147 | bool "Tegra186 family" |
Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 148 | select DM_MAILBOX |
Tom Rini | 5afdcca | 2021-08-19 14:19:39 -0400 | [diff] [blame] | 149 | select GICV2 |
Stephen Warren | 73dd5c4 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 150 | select TEGRA186_BPMP |
Stephen Warren | d9fd700 | 2016-08-08 11:28:24 -0600 | [diff] [blame] | 151 | select TEGRA186_CLOCK |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 152 | select TEGRA186_GPIO |
Stephen Warren | 4dd99d1 | 2016-08-08 11:28:25 -0600 | [diff] [blame] | 153 | select TEGRA186_RESET |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 154 | select TEGRA_ARMV8_COMMON |
Stephen Warren | 0f67e23 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 155 | select TEGRA_HSP |
Stephen Warren | 49626ea | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 156 | select TEGRA_IVC |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 157 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 158 | endchoice |
| 159 | |
Stephen Warren | dd8204d | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 160 | config TEGRA_DISCONNECT_UDC_ON_BOOT |
| 161 | bool "Disconnect USB device mode controller on boot" |
Thierry Reding | 836a56e | 2019-04-15 11:32:26 +0200 | [diff] [blame] | 162 | depends on CI_UDC |
Stephen Warren | dd8204d | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 163 | default y |
| 164 | help |
| 165 | When loading U-Boot into RAM over USB protocols using tools such as |
| 166 | tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device |
| 167 | mode controller is initialized and enumerated by the host PC running |
| 168 | the tool. Unfortunately, these tools do not shut down the USB |
| 169 | controller before executing the downloaded code, and so the host PC |
| 170 | does not "de-enumerate" the USB device. This option shuts down the |
| 171 | USB controller when U-Boot boots to avoid leaving a stale USB device |
| 172 | present. |
| 173 | |
Tom Rini | bd3ef27 | 2022-03-30 18:07:13 -0400 | [diff] [blame] | 174 | config CI_UDC_HAS_HOSTPC |
| 175 | def_bool y |
| 176 | depends on CI_UDC && !TEGRA20 |
| 177 | |
Simon Glass | b724bd7 | 2015-02-11 16:32:59 -0700 | [diff] [blame] | 178 | config SYS_MALLOC_F_LEN |
| 179 | default 0x1800 |
| 180 | |
Masahiro Yamada | 09f455d | 2015-02-20 17:04:04 +0900 | [diff] [blame] | 181 | source "arch/arm/mach-tegra/tegra20/Kconfig" |
| 182 | source "arch/arm/mach-tegra/tegra30/Kconfig" |
| 183 | source "arch/arm/mach-tegra/tegra114/Kconfig" |
| 184 | source "arch/arm/mach-tegra/tegra124/Kconfig" |
Tom Warren | 7aaa5a6 | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 185 | source "arch/arm/mach-tegra/tegra210/Kconfig" |
Stephen Warren | c7ba99c | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 186 | source "arch/arm/mach-tegra/tegra186/Kconfig" |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 187 | |
Tom Rini | d14f3f2 | 2022-12-02 16:42:45 -0500 | [diff] [blame] | 188 | config TEGRA_SPI |
| 189 | def_bool y |
| 190 | depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI |
| 191 | |
| 192 | choice |
| 193 | prompt "UART to use for console" |
| 194 | depends on TEGRA_PINCTRL |
| 195 | default TEGRA_ENABLE_UARTA |
| 196 | |
| 197 | config TEGRA_ENABLE_UARTA |
| 198 | bool "Use UARTA" |
| 199 | |
| 200 | config TEGRA_ENABLE_UARTB |
| 201 | bool "Use UARTB" |
| 202 | |
| 203 | config TEGRA_ENABLE_UARTC |
| 204 | bool "Use UARTC" |
| 205 | |
| 206 | config TEGRA_ENABLE_UARTD |
| 207 | bool "Use UARTD" |
| 208 | |
| 209 | endchoice |
| 210 | |
Tom Rini | 7ef53a3 | 2022-06-08 08:24:33 -0400 | [diff] [blame] | 211 | config TEGRA_GPU |
| 212 | bool "Enable setting up the GPU" |
| 213 | depends on TEGRA124 || TEGRA210 |
| 214 | |
Simon Glass | 42e6f85 | 2017-05-17 03:25:11 -0600 | [diff] [blame] | 215 | config CMD_ENTERRCM |
| 216 | bool "Enable 'enterrcm' command" |
| 217 | default y |
| 218 | help |
| 219 | Tegra's boot ROM supports a mode whereby code may be downloaded and |
| 220 | flash-programmed over a USB connection. On dev boards, this is |
| 221 | typically entered by holding down a "force recovery" button and |
| 222 | resetting the CPU. However, not all boards have such a button (one |
| 223 | example is the Compulab Trimslice), so a method to enter RCM from |
| 224 | software is useful. |
| 225 | |
| 226 | Even on boards other than Trimslice, controlling this over a UART |
| 227 | may be useful, e.g. to allow simple remote control without the need |
| 228 | for mechanical button actuators, or hooking up relays/... to the |
| 229 | button. |
| 230 | |
Ramin Khonsari | 327ff8e | 2023-02-14 19:35:37 +0200 | [diff] [blame] | 231 | config CMD_EBTUPDATE |
| 232 | bool "Enable 'ebtupdate' command" |
Svyatoslav Ryhel | 5a8fe1e | 2023-02-14 19:35:38 +0200 | [diff] [blame] | 233 | depends on TEGRA20 || TEGRA30 |
Ramin Khonsari | 327ff8e | 2023-02-14 19:35:37 +0200 | [diff] [blame] | 234 | select TEGRA_CRYPTO |
| 235 | help |
| 236 | Updating u-boot from within u-boot in rather complex or even |
| 237 | impossible on production devices. To make it easier procedure of |
| 238 | re-cryption was created. If your device was re-crypted choose Y. |
| 239 | |
Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 240 | endif |