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Manivannan Sadhasivamaf8a7352019-08-02 20:40:07 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/hi3660-clock.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/ {
13 compatible = "hisilicon,hi3660";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 psci {
19 compatible = "arm,psci-0.2";
20 method = "smc";
21 };
22
23 cpus {
24 #address-cells = <2>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&cpu0>;
31 };
32 core1 {
33 cpu = <&cpu1>;
34 };
35 core2 {
36 cpu = <&cpu2>;
37 };
38 core3 {
39 cpu = <&cpu3>;
40 };
41 };
42 cluster1 {
43 core0 {
44 cpu = <&cpu4>;
45 };
46 core1 {
47 cpu = <&cpu5>;
48 };
49 core2 {
50 cpu = <&cpu6>;
51 };
52 core3 {
53 cpu = <&cpu7>;
54 };
55 };
56 };
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a53";
60 device_type = "cpu";
61 reg = <0x0 0x0>;
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
65 capacity-dmips-mhz = <592>;
66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
67 operating-points-v2 = <&cluster0_opp>;
68 #cooling-cells = <2>;
69 dynamic-power-coefficient = <110>;
70 };
71
72 cpu1: cpu@1 {
73 compatible = "arm,cortex-a53";
74 device_type = "cpu";
75 reg = <0x0 0x1>;
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
79 capacity-dmips-mhz = <592>;
80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
81 operating-points-v2 = <&cluster0_opp>;
82 #cooling-cells = <2>;
83 };
84
85 cpu2: cpu@2 {
86 compatible = "arm,cortex-a53";
87 device_type = "cpu";
88 reg = <0x0 0x2>;
89 enable-method = "psci";
90 next-level-cache = <&A53_L2>;
91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
92 capacity-dmips-mhz = <592>;
93 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
94 operating-points-v2 = <&cluster0_opp>;
95 #cooling-cells = <2>;
96 };
97
98 cpu3: cpu@3 {
99 compatible = "arm,cortex-a53";
100 device_type = "cpu";
101 reg = <0x0 0x3>;
102 enable-method = "psci";
103 next-level-cache = <&A53_L2>;
104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
105 capacity-dmips-mhz = <592>;
106 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
107 operating-points-v2 = <&cluster0_opp>;
108 #cooling-cells = <2>;
109 };
110
111 cpu4: cpu@100 {
112 compatible = "arm,cortex-a73";
113 device_type = "cpu";
114 reg = <0x0 0x100>;
115 enable-method = "psci";
116 next-level-cache = <&A73_L2>;
117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
118 capacity-dmips-mhz = <1024>;
119 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
120 operating-points-v2 = <&cluster1_opp>;
121 #cooling-cells = <2>;
122 dynamic-power-coefficient = <550>;
123 };
124
125 cpu5: cpu@101 {
126 compatible = "arm,cortex-a73";
127 device_type = "cpu";
128 reg = <0x0 0x101>;
129 enable-method = "psci";
130 next-level-cache = <&A73_L2>;
131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
132 capacity-dmips-mhz = <1024>;
133 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
134 operating-points-v2 = <&cluster1_opp>;
135 #cooling-cells = <2>;
136 };
137
138 cpu6: cpu@102 {
139 compatible = "arm,cortex-a73";
140 device_type = "cpu";
141 reg = <0x0 0x102>;
142 enable-method = "psci";
143 next-level-cache = <&A73_L2>;
144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
145 capacity-dmips-mhz = <1024>;
146 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
147 operating-points-v2 = <&cluster1_opp>;
148 #cooling-cells = <2>;
149 };
150
151 cpu7: cpu@103 {
152 compatible = "arm,cortex-a73";
153 device_type = "cpu";
154 reg = <0x0 0x103>;
155 enable-method = "psci";
156 next-level-cache = <&A73_L2>;
157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
158 capacity-dmips-mhz = <1024>;
159 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
160 operating-points-v2 = <&cluster1_opp>;
161 #cooling-cells = <2>;
162 };
163
164 idle-states {
165 entry-method = "psci";
166
167 CPU_SLEEP_0: cpu-sleep-0 {
168 compatible = "arm,idle-state";
169 local-timer-stop;
170 arm,psci-suspend-param = <0x0010000>;
171 entry-latency-us = <400>;
172 exit-latency-us = <650>;
173 min-residency-us = <1500>;
174 };
175 CLUSTER_SLEEP_0: cluster-sleep-0 {
176 compatible = "arm,idle-state";
177 local-timer-stop;
178 arm,psci-suspend-param = <0x1010000>;
179 entry-latency-us = <500>;
180 exit-latency-us = <1600>;
181 min-residency-us = <3500>;
182 };
183
184
185 CPU_SLEEP_1: cpu-sleep-1 {
186 compatible = "arm,idle-state";
187 local-timer-stop;
188 arm,psci-suspend-param = <0x0010000>;
189 entry-latency-us = <400>;
190 exit-latency-us = <550>;
191 min-residency-us = <1500>;
192 };
193
194 CLUSTER_SLEEP_1: cluster-sleep-1 {
195 compatible = "arm,idle-state";
196 local-timer-stop;
197 arm,psci-suspend-param = <0x1010000>;
198 entry-latency-us = <800>;
199 exit-latency-us = <2900>;
200 min-residency-us = <3500>;
201 };
202 };
203
204 A53_L2: l2-cache0 {
205 compatible = "cache";
206 };
207
208 A73_L2: l2-cache1 {
209 compatible = "cache";
210 };
211 };
212
213 cluster0_opp: opp_table0 {
214 compatible = "operating-points-v2";
215 opp-shared;
216
217 opp00 {
218 opp-hz = /bits/ 64 <533000000>;
219 opp-microvolt = <700000>;
220 clock-latency-ns = <300000>;
221 };
222
223 opp01 {
224 opp-hz = /bits/ 64 <999000000>;
225 opp-microvolt = <800000>;
226 clock-latency-ns = <300000>;
227 };
228
229 opp02 {
230 opp-hz = /bits/ 64 <1402000000>;
231 opp-microvolt = <900000>;
232 clock-latency-ns = <300000>;
233 };
234
235 opp03 {
236 opp-hz = /bits/ 64 <1709000000>;
237 opp-microvolt = <1000000>;
238 clock-latency-ns = <300000>;
239 };
240
241 opp04 {
242 opp-hz = /bits/ 64 <1844000000>;
243 opp-microvolt = <1100000>;
244 clock-latency-ns = <300000>;
245 };
246 };
247
248 cluster1_opp: opp_table1 {
249 compatible = "operating-points-v2";
250 opp-shared;
251
252 opp10 {
253 opp-hz = /bits/ 64 <903000000>;
254 opp-microvolt = <700000>;
255 clock-latency-ns = <300000>;
256 };
257
258 opp11 {
259 opp-hz = /bits/ 64 <1421000000>;
260 opp-microvolt = <800000>;
261 clock-latency-ns = <300000>;
262 };
263
264 opp12 {
265 opp-hz = /bits/ 64 <1805000000>;
266 opp-microvolt = <900000>;
267 clock-latency-ns = <300000>;
268 };
269
270 opp13 {
271 opp-hz = /bits/ 64 <2112000000>;
272 opp-microvolt = <1000000>;
273 clock-latency-ns = <300000>;
274 };
275
276 opp14 {
277 opp-hz = /bits/ 64 <2362000000>;
278 opp-microvolt = <1100000>;
279 clock-latency-ns = <300000>;
280 };
281 };
282
283 gic: interrupt-controller@e82b0000 {
284 compatible = "arm,gic-400";
285 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
286 <0x0 0xe82b2000 0 0x2000>, /* GICC */
287 <0x0 0xe82b4000 0 0x2000>, /* GICH */
288 <0x0 0xe82b6000 0 0x2000>; /* GICV */
289 #address-cells = <0>;
290 #interrupt-cells = <3>;
291 interrupt-controller;
292 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
293 IRQ_TYPE_LEVEL_HIGH)>;
294 };
295
296 a53-pmu {
297 compatible = "arm,cortex-a53-pmu";
298 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-affinity = <&cpu0>,
303 <&cpu1>,
304 <&cpu2>,
305 <&cpu3>;
306 };
307
308 a73-pmu {
309 compatible = "arm,cortex-a73-pmu";
310 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
314 interrupt-affinity = <&cpu4>,
315 <&cpu5>,
316 <&cpu6>,
317 <&cpu7>;
318 };
319
320 timer {
321 compatible = "arm,armv8-timer";
322 interrupt-parent = <&gic>;
323 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
324 IRQ_TYPE_LEVEL_LOW)>,
325 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
326 IRQ_TYPE_LEVEL_LOW)>,
327 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
328 IRQ_TYPE_LEVEL_LOW)>,
329 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
330 IRQ_TYPE_LEVEL_LOW)>;
331 };
332
333 soc {
334 compatible = "simple-bus";
335 #address-cells = <2>;
336 #size-cells = <2>;
337 ranges;
338
339 crg_ctrl: crg_ctrl@fff35000 {
340 compatible = "hisilicon,hi3660-crgctrl", "syscon";
341 reg = <0x0 0xfff35000 0x0 0x1000>;
342 #clock-cells = <1>;
343 };
344
345 crg_rst: crg_rst_controller {
346 compatible = "hisilicon,hi3660-reset";
347 #reset-cells = <2>;
348 hisi,rst-syscon = <&crg_ctrl>;
349 };
350
351
352 pctrl: pctrl@e8a09000 {
353 compatible = "hisilicon,hi3660-pctrl", "syscon";
354 reg = <0x0 0xe8a09000 0x0 0x2000>;
355 #clock-cells = <1>;
356 };
357
358 pmuctrl: crg_ctrl@fff34000 {
359 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
360 reg = <0x0 0xfff34000 0x0 0x1000>;
361 #clock-cells = <1>;
362 };
363
364 sctrl: sctrl@fff0a000 {
365 compatible = "hisilicon,hi3660-sctrl", "syscon";
366 reg = <0x0 0xfff0a000 0x0 0x1000>;
367 #clock-cells = <1>;
368 };
369
370 iomcu: iomcu@ffd7e000 {
371 compatible = "hisilicon,hi3660-iomcu", "syscon";
372 reg = <0x0 0xffd7e000 0x0 0x1000>;
373 #clock-cells = <1>;
374
375 };
376
377 iomcu_rst: reset {
378 compatible = "hisilicon,hi3660-reset";
379 hisi,rst-syscon = <&iomcu>;
380 #reset-cells = <2>;
381 };
382
383 mailbox: mailbox@e896b000 {
384 compatible = "hisilicon,hi3660-mbox";
385 reg = <0x0 0xe896b000 0x0 0x1000>;
386 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
388 #mbox-cells = <3>;
389 };
390
391 stub_clock: stub_clock@e896b500 {
392 compatible = "hisilicon,hi3660-stub-clk";
393 reg = <0x0 0xe896b500 0x0 0x0100>;
394 #clock-cells = <1>;
395 mboxes = <&mailbox 13 3 0>;
396 };
397
398 dual_timer0: timer@fff14000 {
399 compatible = "arm,sp804", "arm,primecell";
400 reg = <0x0 0xfff14000 0x0 0x1000>;
401 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&crg_ctrl HI3660_OSC32K>,
404 <&crg_ctrl HI3660_OSC32K>,
405 <&crg_ctrl HI3660_OSC32K>;
406 clock-names = "timer1", "timer2", "apb_pclk";
407 };
408
409 i2c0: i2c@ffd71000 {
410 compatible = "snps,designware-i2c";
411 reg = <0x0 0xffd71000 0x0 0x1000>;
412 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clock-frequency = <400000>;
416 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
417 resets = <&iomcu_rst 0x20 3>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
420 status = "disabled";
421 };
422
423 i2c1: i2c@ffd72000 {
424 compatible = "snps,designware-i2c";
425 reg = <0x0 0xffd72000 0x0 0x1000>;
426 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 clock-frequency = <400000>;
430 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
431 resets = <&iomcu_rst 0x20 4>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
434 status = "disabled";
435 };
436
437 i2c3: i2c@fdf0c000 {
438 compatible = "snps,designware-i2c";
439 reg = <0x0 0xfdf0c000 0x0 0x1000>;
440 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 clock-frequency = <400000>;
444 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
445 resets = <&crg_rst 0x78 7>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
448 status = "disabled";
449 };
450
451 i2c7: i2c@fdf0b000 {
452 compatible = "snps,designware-i2c";
453 reg = <0x0 0xfdf0b000 0x0 0x1000>;
454 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clock-frequency = <400000>;
458 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
459 resets = <&crg_rst 0x60 14>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
462 status = "disabled";
463 };
464
465 uart0: serial@fdf02000 {
466 compatible = "arm,pl011", "arm,primecell";
467 reg = <0x0 0xfdf02000 0x0 0x1000>;
468 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
470 <&crg_ctrl HI3660_PCLK>;
471 clock-names = "uartclk", "apb_pclk";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
474 status = "disabled";
475 };
476
477 uart1: serial@fdf00000 {
478 compatible = "arm,pl011", "arm,primecell";
479 reg = <0x0 0xfdf00000 0x0 0x1000>;
480 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
481 dma-names = "rx", "tx";
482 dmas = <&dma0 2 &dma0 3>;
483 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
484 <&crg_ctrl HI3660_CLK_GATE_UART1>;
485 clock-names = "uartclk", "apb_pclk";
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
488 status = "disabled";
489 };
490
491 uart2: serial@fdf03000 {
492 compatible = "arm,pl011", "arm,primecell";
493 reg = <0x0 0xfdf03000 0x0 0x1000>;
494 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
495 dma-names = "rx", "tx";
496 dmas = <&dma0 4 &dma0 5>;
497 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
498 <&crg_ctrl HI3660_PCLK>;
499 clock-names = "uartclk", "apb_pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
502 status = "disabled";
503 };
504
505 uart3: serial@ffd74000 {
506 compatible = "arm,pl011", "arm,primecell";
507 reg = <0x0 0xffd74000 0x0 0x1000>;
508 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
510 <&crg_ctrl HI3660_PCLK>;
511 clock-names = "uartclk", "apb_pclk";
512 pinctrl-names = "default";
513 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
514 status = "disabled";
515 };
516
517 uart4: serial@fdf01000 {
518 compatible = "arm,pl011", "arm,primecell";
519 reg = <0x0 0xfdf01000 0x0 0x1000>;
520 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
521 dma-names = "rx", "tx";
522 dmas = <&dma0 6 &dma0 7>;
523 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
524 <&crg_ctrl HI3660_CLK_GATE_UART4>;
525 clock-names = "uartclk", "apb_pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
528 status = "disabled";
529 };
530
531 uart5: serial@fdf05000 {
532 compatible = "arm,pl011", "arm,primecell";
533 reg = <0x0 0xfdf05000 0x0 0x1000>;
534 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
535 dma-names = "rx", "tx";
536 dmas = <&dma0 8 &dma0 9>;
537 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
538 <&crg_ctrl HI3660_CLK_GATE_UART5>;
539 clock-names = "uartclk", "apb_pclk";
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
542 status = "disabled";
543 };
544
545 uart6: serial@fff32000 {
546 compatible = "arm,pl011", "arm,primecell";
547 reg = <0x0 0xfff32000 0x0 0x1000>;
548 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
549 clock = <19200000>;
550 clocks = <&crg_ctrl HI3660_CLK_UART6>,
551 <&crg_ctrl HI3660_PCLK>;
552 clock-names = "uartclk", "apb_pclk";
553 pinctrl-names = "default";
554 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
555 status = "disabled";
556 };
557
558 dma0: dma@fdf30000 {
559 compatible = "hisilicon,k3-dma-1.0";
560 reg = <0x0 0xfdf30000 0x0 0x1000>;
561 #dma-cells = <1>;
562 dma-channels = <16>;
563 dma-requests = <32>;
564 dma-channel-mask = <0xfffe>;
565 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
567 dma-no-cci;
568 dma-type = "hi3660_dma";
569 };
570
571 asp_dmac: dma-controller@e804b000 {
572 compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
573 reg = <0x0 0xe804b000 0x0 0x1000>;
574 #dma-cells = <1>;
575 dma-channels = <16>;
576 dma-requests = <32>;
577 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
578 interrupt-names = "asp_dma_irq";
579 };
580
581 rtc0: rtc@fff04000 {
582 compatible = "arm,pl031", "arm,primecell";
583 reg = <0x0 0Xfff04000 0x0 0x1000>;
584 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&crg_ctrl HI3660_PCLK>;
586 clock-names = "apb_pclk";
587 };
588
589 gpio0: gpio@e8a0b000 {
590 compatible = "arm,pl061", "arm,primecell";
591 reg = <0 0xe8a0b000 0 0x1000>;
592 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 gpio-ranges = <&pmx0 1 0 7>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
599 clock-names = "apb_pclk";
600 };
601
602 gpio1: gpio@e8a0c000 {
603 compatible = "arm,pl061", "arm,primecell";
604 reg = <0 0xe8a0c000 0 0x1000>;
605 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
606 gpio-controller;
607 #gpio-cells = <2>;
608 gpio-ranges = <&pmx0 1 7 7>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
611 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
612 clock-names = "apb_pclk";
613 };
614
615 gpio2: gpio@e8a0d000 {
616 compatible = "arm,pl061", "arm,primecell";
617 reg = <0 0xe8a0d000 0 0x1000>;
618 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
619 gpio-controller;
620 #gpio-cells = <2>;
621 gpio-ranges = <&pmx0 0 14 8>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
625 clock-names = "apb_pclk";
626 };
627
628 gpio3: gpio@e8a0e000 {
629 compatible = "arm,pl061", "arm,primecell";
630 reg = <0 0xe8a0e000 0 0x1000>;
631 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
632 gpio-controller;
633 #gpio-cells = <2>;
634 gpio-ranges = <&pmx0 0 22 8>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
638 clock-names = "apb_pclk";
639 };
640
641 gpio4: gpio@e8a0f000 {
642 compatible = "arm,pl061", "arm,primecell";
643 reg = <0 0xe8a0f000 0 0x1000>;
644 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
645 gpio-controller;
646 #gpio-cells = <2>;
647 gpio-ranges = <&pmx0 0 30 8>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
650 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
651 clock-names = "apb_pclk";
652 };
653
654 gpio5: gpio@e8a10000 {
655 compatible = "arm,pl061", "arm,primecell";
656 reg = <0 0xe8a10000 0 0x1000>;
657 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
658 gpio-controller;
659 #gpio-cells = <2>;
660 gpio-ranges = <&pmx0 0 38 8>;
661 interrupt-controller;
662 #interrupt-cells = <2>;
663 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
664 clock-names = "apb_pclk";
665 };
666
667 gpio6: gpio@e8a11000 {
668 compatible = "arm,pl061", "arm,primecell";
669 reg = <0 0xe8a11000 0 0x1000>;
670 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
671 gpio-controller;
672 #gpio-cells = <2>;
673 gpio-ranges = <&pmx0 0 46 8>;
674 interrupt-controller;
675 #interrupt-cells = <2>;
676 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
677 clock-names = "apb_pclk";
678 };
679
680 gpio7: gpio@e8a12000 {
681 compatible = "arm,pl061", "arm,primecell";
682 reg = <0 0xe8a12000 0 0x1000>;
683 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
684 gpio-controller;
685 #gpio-cells = <2>;
686 gpio-ranges = <&pmx0 0 54 8>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
689 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
690 clock-names = "apb_pclk";
691 };
692
693 gpio8: gpio@e8a13000 {
694 compatible = "arm,pl061", "arm,primecell";
695 reg = <0 0xe8a13000 0 0x1000>;
696 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
697 gpio-controller;
698 #gpio-cells = <2>;
699 gpio-ranges = <&pmx0 0 62 8>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
702 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
703 clock-names = "apb_pclk";
704 };
705
706 gpio9: gpio@e8a14000 {
707 compatible = "arm,pl061", "arm,primecell";
708 reg = <0 0xe8a14000 0 0x1000>;
709 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
710 gpio-controller;
711 #gpio-cells = <2>;
712 gpio-ranges = <&pmx0 0 70 8>;
713 interrupt-controller;
714 #interrupt-cells = <2>;
715 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
716 clock-names = "apb_pclk";
717 };
718
719 gpio10: gpio@e8a15000 {
720 compatible = "arm,pl061", "arm,primecell";
721 reg = <0 0xe8a15000 0 0x1000>;
722 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
723 gpio-controller;
724 #gpio-cells = <2>;
725 gpio-ranges = <&pmx0 0 78 8>;
726 interrupt-controller;
727 #interrupt-cells = <2>;
728 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
729 clock-names = "apb_pclk";
730 };
731
732 gpio11: gpio@e8a16000 {
733 compatible = "arm,pl061", "arm,primecell";
734 reg = <0 0xe8a16000 0 0x1000>;
735 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
736 gpio-controller;
737 #gpio-cells = <2>;
738 gpio-ranges = <&pmx0 0 86 8>;
739 interrupt-controller;
740 #interrupt-cells = <2>;
741 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
742 clock-names = "apb_pclk";
743 };
744
745 gpio12: gpio@e8a17000 {
746 compatible = "arm,pl061", "arm,primecell";
747 reg = <0 0xe8a17000 0 0x1000>;
748 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
749 gpio-controller;
750 #gpio-cells = <2>;
751 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
752 interrupt-controller;
753 #interrupt-cells = <2>;
754 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
755 clock-names = "apb_pclk";
756 };
757
758 gpio13: gpio@e8a18000 {
759 compatible = "arm,pl061", "arm,primecell";
760 reg = <0 0xe8a18000 0 0x1000>;
761 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
762 gpio-controller;
763 #gpio-cells = <2>;
764 gpio-ranges = <&pmx0 0 102 8>;
765 interrupt-controller;
766 #interrupt-cells = <2>;
767 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
768 clock-names = "apb_pclk";
769 };
770
771 gpio14: gpio@e8a19000 {
772 compatible = "arm,pl061", "arm,primecell";
773 reg = <0 0xe8a19000 0 0x1000>;
774 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
775 gpio-controller;
776 #gpio-cells = <2>;
777 gpio-ranges = <&pmx0 0 110 8>;
778 interrupt-controller;
779 #interrupt-cells = <2>;
780 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
781 clock-names = "apb_pclk";
782 };
783
784 gpio15: gpio@e8a1a000 {
785 compatible = "arm,pl061", "arm,primecell";
786 reg = <0 0xe8a1a000 0 0x1000>;
787 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
788 gpio-controller;
789 #gpio-cells = <2>;
790 gpio-ranges = <&pmx0 0 118 6>;
791 interrupt-controller;
792 #interrupt-cells = <2>;
793 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
794 clock-names = "apb_pclk";
795 };
796
797 gpio16: gpio@e8a1b000 {
798 compatible = "arm,pl061", "arm,primecell";
799 reg = <0 0xe8a1b000 0 0x1000>;
800 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
801 gpio-controller;
802 #gpio-cells = <2>;
803 interrupt-controller;
804 #interrupt-cells = <2>;
805 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
806 clock-names = "apb_pclk";
807 };
808
809 gpio17: gpio@e8a1c000 {
810 compatible = "arm,pl061", "arm,primecell";
811 reg = <0 0xe8a1c000 0 0x1000>;
812 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
813 gpio-controller;
814 #gpio-cells = <2>;
815 interrupt-controller;
816 #interrupt-cells = <2>;
817 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
818 clock-names = "apb_pclk";
819 };
820
821 gpio18: gpio@ff3b4000 {
822 compatible = "arm,pl061", "arm,primecell";
823 reg = <0 0xff3b4000 0 0x1000>;
824 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
825 gpio-controller;
826 #gpio-cells = <2>;
827 gpio-ranges = <&pmx2 0 0 8>;
828 interrupt-controller;
829 #interrupt-cells = <2>;
830 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
831 clock-names = "apb_pclk";
832 };
833
834 gpio19: gpio@ff3b5000 {
835 compatible = "arm,pl061", "arm,primecell";
836 reg = <0 0xff3b5000 0 0x1000>;
837 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
838 gpio-controller;
839 #gpio-cells = <2>;
840 gpio-ranges = <&pmx2 0 8 4>;
841 interrupt-controller;
842 #interrupt-cells = <2>;
843 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
844 clock-names = "apb_pclk";
845 };
846
847 gpio20: gpio@e8a1f000 {
848 compatible = "arm,pl061", "arm,primecell";
849 reg = <0 0xe8a1f000 0 0x1000>;
850 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
851 gpio-controller;
852 #gpio-cells = <2>;
853 gpio-ranges = <&pmx1 0 0 6>;
854 interrupt-controller;
855 #interrupt-cells = <2>;
856 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
857 clock-names = "apb_pclk";
858 };
859
860 gpio21: gpio@e8a20000 {
861 compatible = "arm,pl061", "arm,primecell";
862 reg = <0 0xe8a20000 0 0x1000>;
863 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
864 gpio-controller;
865 #gpio-cells = <2>;
866 interrupt-controller;
867 #interrupt-cells = <2>;
868 gpio-ranges = <&pmx3 0 0 6>;
869 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
870 clock-names = "apb_pclk";
871 };
872
873 gpio22: gpio@fff0b000 {
874 compatible = "arm,pl061", "arm,primecell";
875 reg = <0 0xfff0b000 0 0x1000>;
876 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
877 gpio-controller;
878 #gpio-cells = <2>;
879 /* GPIO176 */
880 gpio-ranges = <&pmx4 2 0 6>;
881 interrupt-controller;
882 #interrupt-cells = <2>;
883 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
884 clock-names = "apb_pclk";
885 };
886
887 gpio23: gpio@fff0c000 {
888 compatible = "arm,pl061", "arm,primecell";
889 reg = <0 0xfff0c000 0 0x1000>;
890 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
891 gpio-controller;
892 #gpio-cells = <2>;
893 /* GPIO184 */
894 gpio-ranges = <&pmx4 0 6 7>;
895 interrupt-controller;
896 #interrupt-cells = <2>;
897 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
898 clock-names = "apb_pclk";
899 };
900
901 gpio24: gpio@fff0d000 {
902 compatible = "arm,pl061", "arm,primecell";
903 reg = <0 0xfff0d000 0 0x1000>;
904 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
905 gpio-controller;
906 #gpio-cells = <2>;
907 /* GPIO192 */
908 gpio-ranges = <&pmx4 0 13 8>;
909 interrupt-controller;
910 #interrupt-cells = <2>;
911 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
912 clock-names = "apb_pclk";
913 };
914
915 gpio25: gpio@fff0e000 {
916 compatible = "arm,pl061", "arm,primecell";
917 reg = <0 0xfff0e000 0 0x1000>;
918 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
919 gpio-controller;
920 #gpio-cells = <2>;
921 /* GPIO200 */
922 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
923 interrupt-controller;
924 #interrupt-cells = <2>;
925 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
926 clock-names = "apb_pclk";
927 };
928
929 gpio26: gpio@fff0f000 {
930 compatible = "arm,pl061", "arm,primecell";
931 reg = <0 0xfff0f000 0 0x1000>;
932 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
933 gpio-controller;
934 #gpio-cells = <2>;
935 /* GPIO208 */
936 gpio-ranges = <&pmx4 0 28 8>;
937 interrupt-controller;
938 #interrupt-cells = <2>;
939 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
940 clock-names = "apb_pclk";
941 };
942
943 gpio27: gpio@fff10000 {
944 compatible = "arm,pl061", "arm,primecell";
945 reg = <0 0xfff10000 0 0x1000>;
946 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
947 gpio-controller;
948 #gpio-cells = <2>;
949 /* GPIO216 */
950 gpio-ranges = <&pmx4 0 36 6>;
951 interrupt-controller;
952 #interrupt-cells = <2>;
953 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
954 clock-names = "apb_pclk";
955 };
956
957 gpio28: gpio@fff1d000 {
958 compatible = "arm,pl061", "arm,primecell";
959 reg = <0 0xfff1d000 0 0x1000>;
960 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
961 gpio-controller;
962 #gpio-cells = <2>;
963 interrupt-controller;
964 #interrupt-cells = <2>;
965 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
966 clock-names = "apb_pclk";
967 };
968
969 spi2: spi@ffd68000 {
970 compatible = "arm,pl022", "arm,primecell";
971 reg = <0x0 0xffd68000 0x0 0x1000>;
972 #address-cells = <1>;
973 #size-cells = <0>;
974 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
976 clock-names = "apb_pclk";
977 pinctrl-names = "default";
978 pinctrl-0 = <&spi2_pmx_func>;
979 num-cs = <1>;
980 cs-gpios = <&gpio27 2 0>;
981 status = "disabled";
982 };
983
984 spi3: spi@ff3b3000 {
985 compatible = "arm,pl022", "arm,primecell";
986 reg = <0x0 0xff3b3000 0x0 0x1000>;
987 #address-cells = <1>;
988 #size-cells = <0>;
989 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
991 clock-names = "apb_pclk";
992 pinctrl-names = "default";
993 pinctrl-0 = <&spi3_pmx_func>;
994 num-cs = <1>;
995 cs-gpios = <&gpio18 5 0>;
996 status = "disabled";
997 };
998
999 pcie@f4000000 {
1000 compatible = "hisilicon,kirin960-pcie";
1001 reg = <0x0 0xf4000000 0x0 0x1000>,
1002 <0x0 0xff3fe000 0x0 0x1000>,
1003 <0x0 0xf3f20000 0x0 0x40000>,
1004 <0x0 0xf5000000 0x0 0x2000>;
1005 reg-names = "dbi", "apb", "phy", "config";
1006 bus-range = <0x0 0x1>;
1007 #address-cells = <3>;
1008 #size-cells = <2>;
1009 device_type = "pci";
1010 ranges = <0x02000000 0x0 0x00000000
1011 0x0 0xf6000000
1012 0x0 0x02000000>;
1013 num-lanes = <1>;
1014 #interrupt-cells = <1>;
1015 interrupts = <0 283 4>;
1016 interrupt-names = "msi";
1017 interrupt-map-mask = <0xf800 0 0 7>;
1018 interrupt-map = <0x0 0 0 1
1019 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1020 <0x0 0 0 2
1021 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1022 <0x0 0 0 3
1023 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1024 <0x0 0 0 4
1025 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1027 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1028 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1029 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1030 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1031 clock-names = "pcie_phy_ref", "pcie_aux",
1032 "pcie_apb_phy", "pcie_apb_sys",
1033 "pcie_aclk";
1034 reset-gpios = <&gpio11 1 0 >;
1035 };
1036
1037 /* UFS */
1038 ufs: ufs@ff3b0000 {
1039 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1040 /* 0: HCI standard */
1041 /* 1: UFS SYS CTRL */
1042 reg = <0x0 0xff3b0000 0x0 0x1000>,
1043 <0x0 0xff3b1000 0x0 0x1000>;
1044 interrupt-parent = <&gic>;
1045 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1047 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1048 clock-names = "ref_clk", "phy_clk";
1049 freq-table-hz = <0 0>, <0 0>;
1050 /* offset: 0x84; bit: 12 */
1051 resets = <&crg_rst 0x84 12>;
1052 reset-names = "rst";
1053 };
1054
1055 /* SD */
1056 dwmmc1: dwmmc1@ff37f000 {
1057 compatible = "hisilicon,hi3660-dw-mshc";
1058 reg = <0x0 0xff37f000 0x0 0x1000>;
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1063 <&crg_ctrl HI3660_HCLK_GATE_SD>;
1064 clock-names = "ciu", "biu";
1065 clock-frequency = <3200000>;
1066 resets = <&crg_rst 0x94 18>;
1067 reset-names = "reset";
1068 hisilicon,peripheral-syscon = <&sctrl>;
1069 card-detect-delay = <200>;
1070 status = "disabled";
1071 };
1072
1073 /* SDIO */
1074 dwmmc2: dwmmc2@ff3ff000 {
1075 compatible = "hisilicon,hi3660-dw-mshc";
1076 reg = <0x0 0xff3ff000 0x0 0x1000>;
1077 #address-cells = <0x1>;
1078 #size-cells = <0x0>;
1079 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1081 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1082 clock-names = "ciu", "biu";
1083 resets = <&crg_rst 0x94 20>;
1084 reset-names = "reset";
1085 card-detect-delay = <200>;
1086 status = "disabled";
1087 };
1088
1089 watchdog0: watchdog@e8a06000 {
1090 compatible = "arm,sp805-wdt", "arm,primecell";
1091 reg = <0x0 0xe8a06000 0x0 0x1000>;
1092 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&crg_ctrl HI3660_OSC32K>;
1094 clock-names = "apb_pclk";
1095 };
1096
1097 watchdog1: watchdog@e8a07000 {
1098 compatible = "arm,sp805-wdt", "arm,primecell";
1099 reg = <0x0 0xe8a07000 0x0 0x1000>;
1100 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1101 clocks = <&crg_ctrl HI3660_OSC32K>;
1102 clock-names = "apb_pclk";
1103 };
1104
1105 tsensor: tsensor@fff30000 {
1106 compatible = "hisilicon,hi3660-tsensor";
1107 reg = <0x0 0xfff30000 0x0 0x1000>;
1108 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1109 #thermal-sensor-cells = <1>;
1110 };
1111
1112 thermal-zones {
1113
1114 cls0: cls0 {
1115 polling-delay = <1000>;
1116 polling-delay-passive = <100>;
1117 sustainable-power = <4500>;
1118
1119 /* sensor ID */
1120 thermal-sensors = <&tsensor 1>;
1121
1122 trips {
1123 threshold: trip-point@0 {
1124 temperature = <65000>;
1125 hysteresis = <1000>;
1126 type = "passive";
1127 };
1128
1129 target: trip-point@1 {
1130 temperature = <75000>;
1131 hysteresis = <1000>;
1132 type = "passive";
1133 };
1134 };
1135
1136 cooling-maps {
1137 map0 {
1138 trip = <&target>;
1139 contribution = <1024>;
1140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1141 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1142 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1143 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1144 };
1145 map1 {
1146 trip = <&target>;
1147 contribution = <512>;
1148 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1149 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1150 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1151 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1152 };
1153 };
1154 };
1155 };
1156 };
1157};