blob: 8a864ba3ed3f7c058743d569d1e5466e24eb5028 [file] [log] [blame]
Ashok Reddy Soma37688da2023-06-14 06:13:51 -06001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal NET Mini eMMC Configuration
4 *
5 * (C) Copyright 2023, Advanced Micro Devices, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 * Ashok Reddy Soma <ashok.reddy.soma@amd.com>
9 */
10
11/dts-v1/;
12
13/ {
14 compatible = "xlnx,versal-net-mini";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 model = "Xilinx Versal NET MINI eMMC";
18
19 aliases {
20 serial0 = &dcc;
21 mmc0 = &sdhci1;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200";
26 };
27
28 memory@0 {
29 device_type = "memory";
30 reg = <0 0 0 0x20000000>;
31 };
32
33 clk200: clk200 {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <200000000>;
37 };
38
39 dcc: dcc {
40 compatible = "arm,dcc";
41 status = "okay";
42 bootph-all;
43 };
44
45 amba: amba {
46 bootph-all;
47 compatible = "simple-bus";
48 #address-cells = <2>;
49 #size-cells = <2>;
50 ranges;
51
52 sdhci1: sdhci@f1050000 {
53 compatible = "xlnx,versal-net-emmc";
54 status = "okay";
55 non-removable;
56 disable-wp;
57 bus-width = <8>;
58 reg = <0 0xf1050000 0 0x10000>;
59 clock-names = "clk_xin", "clk_ahb";
60 clocks = <&clk200>, <&clk200>;
61 xlnx,mio-bank = <0>;
62 };
63 };
64};