blob: 34142302445e1a378381b902118bb65ca34b1a3e [file] [log] [blame]
Peter Tyser5da6f802009-06-30 17:26:01 -05001/*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Peter Tyser5da6f802009-06-30 17:26:01 -05006 */
7
8/*
Peter Tyserc00ac252010-10-22 00:20:26 -05009 * xpedite517x board configuration file
Peter Tyser5da6f802009-06-30 17:26:01 -050010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
Peter Tyser5da6f802009-06-30 17:26:01 -050017#define CONFIG_MPC8641 1 /* MPC8641 specific */
18#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
19#define CONFIG_SYS_BOARD_NAME "XPedite5170"
John Schmoller92af65492010-10-22 00:20:24 -050020#define CONFIG_SYS_FORM_3U_VPX 1
Peter Tyser5da6f802009-06-30 17:26:01 -050021#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050023#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Peter Tyser5da6f802009-06-30 17:26:01 -050024#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
25#define CONFIG_ALTIVEC 1
John Schmoller02851002015-01-09 15:42:50 -060026#define CONFIG_SYS_GENERIC_BOARD
27#define CONFIG_DISPLAY_BOARDINFO
Peter Tyser5da6f802009-06-30 17:26:01 -050028
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xfff00000
30
Peter Tyser5da6f802009-06-30 17:26:01 -050031#define CONFIG_PCI 1 /* Enable PCI/PCIE */
32#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
33#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
34#define CONFIG_PCIE1 1 /* PCIE controler 1 */
35#define CONFIG_PCIE2 1 /* PCIE controler 2 */
36#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000037#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Peter Tyser5da6f802009-06-30 17:26:01 -050038#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
39#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
40
41/*
42 * DDR config
43 */
York Sun5614e712013-09-30 09:22:09 -070044#define CONFIG_SYS_FSL_DDR2
Peter Tyser5da6f802009-06-30 17:26:01 -050045#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
46#define CONFIG_DDR_SPD
47#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
48#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
49#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
50#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
51#define CONFIG_NUM_DDR_CONTROLLERS 2
52#define CONFIG_DIMM_SLOTS_PER_CTLR 1
53#define CONFIG_CHIP_SELECTS_PER_CTRL 1
54#define CONFIG_DDR_ECC
55#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
56#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
57#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
58#define CONFIG_VERY_BIG_RAM
59#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
60
61/*
62 * virtual address to be used for temporary mappings. There
63 * should be 128k free at this VA.
64 */
65#define CONFIG_SYS_SCRATCH_VA 0xe0000000
66
67#ifndef __ASSEMBLY__
68extern unsigned long get_board_sys_clk(unsigned long dummy);
69#endif
70
71#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
72
73/*
74 * L2CR setup
75 */
76#define CONFIG_SYS_L2
77#define L2_INIT 0
78#define L2_ENABLE (L2CR_L2E)
79
80/*
81 * Base addresses -- Note these are effective addresses where the
82 * actual resources get mapped (not physical addresses)
83 */
84#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
85#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
86#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
87#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
88#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
89#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
Peter Tyser5da6f802009-06-30 17:26:01 -050090
91/*
92 * Diagnostics
93 */
94#define CONFIG_SYS_ALT_MEMTEST
95#define CONFIG_SYS_MEMTEST_START 0x10000000
96#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tyser66a8b442010-10-22 00:20:33 -050097#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
98 CONFIG_SYS_POST_I2C)
99#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
100 CONFIG_SYS_I2C_DS4510_ADDR, \
101 CONFIG_SYS_I2C_EEPROM_ADDR, \
102 CONFIG_SYS_I2C_LM90_ADDR, \
103 CONFIG_SYS_I2C_PCA9553_ADDR, \
104 CONFIG_SYS_I2C_PCA953X_ADDR0, \
105 CONFIG_SYS_I2C_PCA953X_ADDR1, \
106 CONFIG_SYS_I2C_PCA953X_ADDR2, \
107 CONFIG_SYS_I2C_PCA953X_ADDR3, \
108 CONFIG_SYS_I2C_PEX8518_ADDR, \
109 CONFIG_SYS_I2C_RTC_ADDR}
110/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
111#define I2C_ADDR_IGNORE_LIST {0x50}
Peter Tyser5da6f802009-06-30 17:26:01 -0500112
113/*
114 * Memory map
115 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
116 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
117 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
118 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
119 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
120 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
121 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
122 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
123 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
124 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
125 */
126
Kumar Gala202d9482009-09-15 22:21:58 -0500127#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
Peter Tyser5da6f802009-06-30 17:26:01 -0500128
129/*
130 * NAND flash configuration
131 */
132#define CONFIG_SYS_NAND_BASE 0xef800000
133#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
134#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
135#define CONFIG_SYS_MAX_NAND_DEVICE 2
136#define CONFIG_NAND_ACTL
137#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
138#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
139#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
140#define CONFIG_SYS_NAND_ACTL_DELAY 25
141#define CONFIG_SYS_NAND_QUIET_TEST
142#define CONFIG_JFFS2_NAND
143
144/*
145 * NOR flash configuration
146 */
147#define CONFIG_SYS_FLASH_BASE 0xf8000000
148#define CONFIG_SYS_FLASH_BASE2 0xf0000000
149#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
150#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
151#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
152#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
153#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
154#define CONFIG_FLASH_CFI_DRIVER
155#define CONFIG_SYS_FLASH_CFI
156#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
157#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
158 {0xf7f00000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyser5da6f802009-06-30 17:26:01 -0500160#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
161
162/*
163 * Chip select configuration
164 */
165/* NOR Flash 0 on CS0 */
166#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
167 BR_PS_16 |\
168 BR_V)
169#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
170 OR_GPCM_CSNT |\
171 OR_GPCM_XACS |\
172 OR_GPCM_ACS_DIV2 |\
173 OR_GPCM_SCY_8 |\
174 OR_GPCM_TRLX |\
175 OR_GPCM_EHTR |\
176 OR_GPCM_EAD)
177
178/* NOR Flash 1 on CS1 */
179#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
180 BR_PS_16 |\
181 BR_V)
182#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
183
184/* NAND flash on CS2 */
185#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
186 BR_PS_8 |\
187 BR_V)
188#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
189 OR_GPCM_BCTLD |\
190 OR_GPCM_CSNT |\
191 OR_GPCM_ACS_DIV4 |\
192 OR_GPCM_SCY_4 |\
193 OR_GPCM_TRLX |\
194 OR_GPCM_EHTR)
195
196/* Optional NAND flash on CS3 */
197#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
198 BR_PS_8 |\
199 BR_V)
200#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
201
202/*
203 * Use L1 as initial stack
204 */
205#define CONFIG_SYS_INIT_RAM_LOCK 1
206#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200207#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Peter Tyser5da6f802009-06-30 17:26:01 -0500208
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200209#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyser5da6f802009-06-30 17:26:01 -0500210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211
212#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
213#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
214
215/*
216 * Serial Port
217 */
218#define CONFIG_CONS_INDEX 1
219#define CONFIG_SYS_NS16550
220#define CONFIG_SYS_NS16550_SERIAL
221#define CONFIG_SYS_NS16550_REG_SIZE 1
222#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
223#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
224#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
225#define CONFIG_SYS_BAUDRATE_TABLE \
226 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
227#define CONFIG_BAUDRATE 115200
228#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
229#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
230
231/*
232 * Use the HUSH parser
233 */
234#define CONFIG_SYS_HUSH_PARSER
Peter Tyser5da6f802009-06-30 17:26:01 -0500235
236/*
237 * Pass open firmware flat tree
238 */
239#define CONFIG_OF_LIBFDT 1
240#define CONFIG_OF_BOARD_SETUP 1
241#define CONFIG_OF_STDOUT_VIA_ALIAS 1
242
Peter Tyser5da6f802009-06-30 17:26:01 -0500243/*
244 * I2C
245 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200246#define CONFIG_SYS_I2C
247#define CONFIG_SYS_I2C_FSL
248#define CONFIG_SYS_FSL_I2C_SPEED 100000
249#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
250#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
251#define CONFIG_SYS_FSL_I2C2_SPEED 100000
252#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
253#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Peter Tyser5da6f802009-06-30 17:26:01 -0500254
255/* PEX8518 slave I2C interface */
256#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
257
258/* I2C DS1631 temperature sensor */
259#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
260#define CONFIG_DTT_DS1621
261#define CONFIG_DTT_SENSORS { 0 }
Peter Tyser66a8b442010-10-22 00:20:33 -0500262#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
Peter Tyser5da6f802009-06-30 17:26:01 -0500263
264/* I2C EEPROM - AT24C128B */
265#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
266#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
267#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
268#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
269
270/* I2C RTC */
271#define CONFIG_RTC_M41T11 1
272#define CONFIG_SYS_I2C_RTC_ADDR 0x68
273#define CONFIG_SYS_M41T11_BASE_YEAR 2000
274
275/* GPIO/EEPROM/SRAM */
276#define CONFIG_DS4510
277#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
278
279/* GPIO */
280#define CONFIG_PCA953X
281#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
282#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
283#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
284#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
285#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
Peter Tyser66a8b442010-10-22 00:20:33 -0500286#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
Peter Tyser5da6f802009-06-30 17:26:01 -0500287
288/*
289 * PU = pulled high, PD = pulled low
290 * I = input, O = output, IO = input/output
291 */
292/* PCA9557 @ 0x18*/
293#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
294#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
295#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
296#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
297#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
298#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
299
300/* PCA9557 @ 0x1c*/
301#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
302#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
303#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
304#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
305#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
306#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
307#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
308#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
309
310/* PCA9557 @ 0x1e*/
311#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
312#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
313#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
314#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
315#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
316#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
317#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
318
319/* PCA9557 @ 0x1f */
320#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
321#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
322#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
323#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
324
325/*
326 * General PCI
327 * Memory space is mapped 1-1, but I/O space must start from 0.
328 */
329/* PCIE1 - PEX8518 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500330#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
331#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500332#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500333#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Peter Tyser5da6f802009-06-30 17:26:01 -0500334#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
335#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
336
337/* PCIE2 - VPX P1 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500338#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
339#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500340#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500341#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Peter Tyser5da6f802009-06-30 17:26:01 -0500342#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
343#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
344
345/*
346 * Networking options
347 */
348#define CONFIG_TSEC_ENET /* tsec ethernet support */
349#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Peter Tyser5da6f802009-06-30 17:26:01 -0500350#define CONFIG_MII 1 /* MII PHY management */
351#define CONFIG_ETHPRIME "eTSEC1"
352
353#define CONFIG_TSEC1 1
354#define CONFIG_TSEC1_NAME "eTSEC1"
355#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
356#define TSEC1_PHY_ADDR 1
357#define TSEC1_PHYIDX 0
358#define CONFIG_HAS_ETH0
359
360#define CONFIG_TSEC2 1
361#define CONFIG_TSEC2_NAME "eTSEC2"
362#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
363#define TSEC2_PHY_ADDR 2
364#define TSEC2_PHYIDX 0
365#define CONFIG_HAS_ETH1
366
367/*
368 * BAT mappings
369 */
370#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
371#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
372 BATL_PP_RW |\
373 BATL_CACHEINHIBIT |\
374 BATL_GUARDEDSTORAGE)
375#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
376 BATU_BL_1M |\
377 BATU_VS |\
378 BATU_VP)
379#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
380 BATL_PP_RW |\
381 BATL_CACHEINHIBIT)
382#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
383#endif
384
385/*
386 * BAT0 2G Cacheable, non-guarded
387 * 0x0000_0000 2G DDR
388 */
389#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
390#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
391#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
392#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
393
394/*
395 * BAT1 1G Cache-inhibited, guarded
396 * 0x8000_0000 1G PCI-Express 1 Memory
397 */
398#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
399 BATL_PP_RW |\
400 BATL_CACHEINHIBIT |\
401 BATL_GUARDEDSTORAGE)
402#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
403 BATU_BL_1G |\
404 BATU_VS |\
405 BATU_VP)
406#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
407 BATL_PP_RW |\
408 BATL_CACHEINHIBIT)
409#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
410
411/*
412 * BAT2 512M Cache-inhibited, guarded
413 * 0xc000_0000 512M PCI-Express 2 Memory
414 */
415#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
416 BATL_PP_RW |\
417 BATL_CACHEINHIBIT |\
418 BATL_GUARDEDSTORAGE)
419#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
420 BATU_BL_512M |\
421 BATU_VS |\
422 BATU_VP)
423#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
424 BATL_PP_RW |\
425 BATL_CACHEINHIBIT)
426#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
427
428/*
429 * BAT3 1M Cache-inhibited, guarded
430 * 0xe000_0000 1M CCSR
431 */
432#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
433 BATL_PP_RW |\
434 BATL_CACHEINHIBIT |\
435 BATL_GUARDEDSTORAGE)
436#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
437 BATU_BL_1M |\
438 BATU_VS |\
439 BATU_VP)
440#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
441 BATL_PP_RW |\
442 BATL_CACHEINHIBIT)
443#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
444
445/*
446 * BAT4 32M Cache-inhibited, guarded
447 * 0xe200_0000 16M PCI-Express 1 I/O
448 * 0xe300_0000 16M PCI-Express 2 I/0
449 */
450#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
451 BATL_PP_RW |\
452 BATL_CACHEINHIBIT |\
453 BATL_GUARDEDSTORAGE)
454#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
455 BATU_BL_32M |\
456 BATU_VS |\
457 BATU_VP)
458#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
459 BATL_PP_RW |\
460 BATL_CACHEINHIBIT)
461#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
462
463/*
464 * BAT5 128K Cacheable, non-guarded
465 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
466 */
467#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
468 BATL_PP_RW |\
469 BATL_MEMCOHERENCE)
470#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
471 BATU_BL_128K |\
472 BATU_VS |\
473 BATU_VP)
474#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
475#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
476
477/*
478 * BAT6 256M Cache-inhibited, guarded
479 * 0xf000_0000 256M FLASH
480 */
481#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
482 BATL_PP_RW |\
483 BATL_CACHEINHIBIT |\
484 BATL_GUARDEDSTORAGE)
485#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
486 BATU_BL_256M |\
487 BATU_VS |\
488 BATU_VP)
489#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
490 BATL_PP_RW |\
491 BATL_MEMCOHERENCE)
492#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
493
494/* Map the last 1M of flash where we're running from reset */
495#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
496 BATL_PP_RW |\
497 BATL_CACHEINHIBIT |\
498 BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200499#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
Peter Tyser5da6f802009-06-30 17:26:01 -0500500 BATU_BL_1M |\
501 BATU_VS |\
502 BATU_VP)
503#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
504 BATL_PP_RW |\
505 BATL_MEMCOHERENCE)
506#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
507
508/*
509 * BAT7 64M Cache-inhibited, guarded
510 * 0xe800_0000 64K NAND FLASH
511 * 0xe804_0000 128K DUART Registers
512 */
513#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
514 BATL_PP_RW |\
515 BATL_CACHEINHIBIT |\
516 BATL_GUARDEDSTORAGE)
517#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
518 BATU_BL_512K |\
519 BATU_VS |\
520 BATU_VP)
521#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
522 BATL_PP_RW |\
523 BATL_CACHEINHIBIT)
524#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
525
526/*
527 * Command configuration.
528 */
529#include <config_cmd_default.h>
530
531#define CONFIG_CMD_ASKENV
532#define CONFIG_CMD_DATE
533#define CONFIG_CMD_DHCP
534#define CONFIG_CMD_DS4510
535#define CONFIG_CMD_DS4510_INFO
536#define CONFIG_CMD_DTT
537#define CONFIG_CMD_EEPROM
538#define CONFIG_CMD_ELF
539#define CONFIG_CMD_SAVEENV
540#define CONFIG_CMD_FLASH
541#define CONFIG_CMD_I2C
542#define CONFIG_CMD_IRQ
543#define CONFIG_CMD_JFFS2
544#define CONFIG_CMD_MII
545#define CONFIG_CMD_NAND
546#define CONFIG_CMD_NET
547#define CONFIG_CMD_PCA953X
548#define CONFIG_CMD_PCA953X_INFO
549#define CONFIG_CMD_PCI
John Schmoller96d61602010-10-22 00:20:23 -0500550#define CONFIG_CMD_PCI_ENUM
Peter Tyser5da6f802009-06-30 17:26:01 -0500551#define CONFIG_CMD_PING
552#define CONFIG_CMD_REGINFO
553#define CONFIG_CMD_SNTP
554
555/*
556 * Miscellaneous configurable options
557 */
558#define CONFIG_SYS_LONGHELP /* undef to save memory */
559#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Peter Tyser5da6f802009-06-30 17:26:01 -0500560#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
561#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
562#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
563#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Peter Tyser5da6f802009-06-30 17:26:01 -0500564#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
565#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
566#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
567#define CONFIG_PANIC_HANG /* do not reset board on panic */
568#define CONFIG_PREBOOT /* enable preboot variable */
569#define CONFIG_FIT 1
570#define CONFIG_FIT_VERBOSE 1
571#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
572
573/*
574 * For booting Linux, the board info and command line data
575 * have to be in the first 16 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
577 */
578#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500579#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser5da6f802009-06-30 17:26:01 -0500580
581/*
Peter Tyser5da6f802009-06-30 17:26:01 -0500582 * Environment Configuration
583 */
584#define CONFIG_ENV_IS_IN_FLASH 1
585#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
586#define CONFIG_ENV_SIZE 0x8000
587#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
588
589/*
590 * Flash memory map:
591 * fffc0000 - ffffffff Pri FDT (256KB)
592 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
593 * fff00000 - fff7ffff Pri U-Boot (512 KB)
594 * fef00000 - ffefffff Pri OS image (16MB)
595 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
596 *
597 * f7fc0000 - f7ffffff Sec FDT (256KB)
598 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
599 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
600 * f6f00000 - f7efffff Sec OS image (16MB)
601 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
602 */
Marek Vasut5368c552012-09-23 17:41:24 +0200603#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
604#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
605#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
606#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
607#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
608#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
Peter Tyser5da6f802009-06-30 17:26:01 -0500609
610#define CONFIG_PROG_UBOOT1 \
611 "$download_cmd $loadaddr $ubootfile; " \
612 "if test $? -eq 0; then " \
613 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
614 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
615 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
616 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
617 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
618 "if test $? -ne 0; then " \
619 "echo PROGRAM FAILED; " \
620 "else; " \
621 "echo PROGRAM SUCCEEDED; " \
622 "fi; " \
623 "else; " \
624 "echo DOWNLOAD FAILED; " \
625 "fi;"
626
627#define CONFIG_PROG_UBOOT2 \
628 "$download_cmd $loadaddr $ubootfile; " \
629 "if test $? -eq 0; then " \
630 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
631 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
632 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
633 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
634 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
635 "if test $? -ne 0; then " \
636 "echo PROGRAM FAILED; " \
637 "else; " \
638 "echo PROGRAM SUCCEEDED; " \
639 "fi; " \
640 "else; " \
641 "echo DOWNLOAD FAILED; " \
642 "fi;"
643
644#define CONFIG_BOOT_OS_NET \
645 "$download_cmd $osaddr $osfile; " \
646 "if test $? -eq 0; then " \
647 "if test -n $fdtaddr; then " \
648 "$download_cmd $fdtaddr $fdtfile; " \
649 "if test $? -eq 0; then " \
650 "bootm $osaddr - $fdtaddr; " \
651 "else; " \
652 "echo FDT DOWNLOAD FAILED; " \
653 "fi; " \
654 "else; " \
655 "bootm $osaddr; " \
656 "fi; " \
657 "else; " \
658 "echo OS DOWNLOAD FAILED; " \
659 "fi;"
660
661#define CONFIG_PROG_OS1 \
662 "$download_cmd $osaddr $osfile; " \
663 "if test $? -eq 0; then " \
664 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
665 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
666 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
667 "if test $? -ne 0; then " \
668 "echo OS PROGRAM FAILED; " \
669 "else; " \
670 "echo OS PROGRAM SUCCEEDED; " \
671 "fi; " \
672 "else; " \
673 "echo OS DOWNLOAD FAILED; " \
674 "fi;"
675
676#define CONFIG_PROG_OS2 \
677 "$download_cmd $osaddr $osfile; " \
678 "if test $? -eq 0; then " \
679 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
680 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
681 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
682 "if test $? -ne 0; then " \
683 "echo OS PROGRAM FAILED; " \
684 "else; " \
685 "echo OS PROGRAM SUCCEEDED; " \
686 "fi; " \
687 "else; " \
688 "echo OS DOWNLOAD FAILED; " \
689 "fi;"
690
691#define CONFIG_PROG_FDT1 \
692 "$download_cmd $fdtaddr $fdtfile; " \
693 "if test $? -eq 0; then " \
694 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
695 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
696 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
697 "if test $? -ne 0; then " \
698 "echo FDT PROGRAM FAILED; " \
699 "else; " \
700 "echo FDT PROGRAM SUCCEEDED; " \
701 "fi; " \
702 "else; " \
703 "echo FDT DOWNLOAD FAILED; " \
704 "fi;"
705
706#define CONFIG_PROG_FDT2 \
707 "$download_cmd $fdtaddr $fdtfile; " \
708 "if test $? -eq 0; then " \
709 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
710 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
711 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
712 "if test $? -ne 0; then " \
713 "echo FDT PROGRAM FAILED; " \
714 "else; " \
715 "echo FDT PROGRAM SUCCEEDED; " \
716 "fi; " \
717 "else; " \
718 "echo FDT DOWNLOAD FAILED; " \
719 "fi;"
720
721#define CONFIG_EXTRA_ENV_SETTINGS \
722 "autoload=yes\0" \
723 "download_cmd=tftp\0" \
724 "console_args=console=ttyS0,115200\0" \
725 "root_args=root=/dev/nfs rw\0" \
726 "misc_args=ip=on\0" \
727 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
728 "bootfile=/home/user/file\0" \
Peter Tyserc00ac252010-10-22 00:20:26 -0500729 "osfile=/home/user/board.uImage\0" \
730 "fdtfile=/home/user/board.dtb\0" \
Peter Tyser5da6f802009-06-30 17:26:01 -0500731 "ubootfile=/home/user/u-boot.bin\0" \
732 "fdtaddr=c00000\0" \
733 "osaddr=0x1000000\0" \
734 "loadaddr=0x1000000\0" \
735 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
736 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
737 "prog_os1="CONFIG_PROG_OS1"\0" \
738 "prog_os2="CONFIG_PROG_OS2"\0" \
739 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
740 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
741 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
742 "bootcmd_flash1=run set_bootargs; " \
743 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
744 "bootcmd_flash2=run set_bootargs; " \
745 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
746 "bootcmd=run bootcmd_flash1\0"
747#endif /* __CONFIG_H */