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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * linux/arch/ppc/kernel/traps.c
3 *
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * (C) Copyright 2000
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31/*
32 * This file handles the architecture-dependent parts of hardware exceptions
33 */
34
35#include <common.h>
36#include <command.h>
37#include <asm/processor.h>
38
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020039DECLARE_GLOBAL_DATA_PTR;
40
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -050041#if defined(CONFIG_CMD_KGDB)
wdenkaffae2b2002-08-17 09:36:01 +000042int (*debugger_exception_handler)(struct pt_regs *) = 0;
43#endif
44
45/* Returns 0 if exception not found and fixup otherwise. */
46extern unsigned long search_exception_table(unsigned long);
47
48/* THIS NEEDS CHANGING to use the board info structure.
49 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020050#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
wdenkaffae2b2002-08-17 09:36:01 +000051
52static __inline__ void set_tsr(unsigned long val)
53{
54#if defined(CONFIG_440)
55 asm volatile("mtspr 0x150, %0" : : "r" (val));
56#else
57 asm volatile("mttsr %0" : : "r" (val));
58#endif
59}
60
61static __inline__ unsigned long get_esr(void)
62{
63 unsigned long val;
64
65#if defined(CONFIG_440)
66 asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
67#else
68 asm volatile("mfesr %0" : "=r" (val) :);
69#endif
70 return val;
71}
72
73#define ESR_MCI 0x80000000
74#define ESR_PIL 0x08000000
75#define ESR_PPR 0x04000000
76#define ESR_PTR 0x02000000
77#define ESR_DST 0x00800000
78#define ESR_DIZ 0x00400000
79#define ESR_U0F 0x00008000
80
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -050081#if defined(CONFIG_CMD_BEDBUG)
wdenkaffae2b2002-08-17 09:36:01 +000082extern void do_bedbug_breakpoint(struct pt_regs *);
83#endif
84
85/*
86 * Trap & Exception support
87 */
88
89void
90print_backtrace(unsigned long *sp)
91{
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020092 int cnt = 0;
93 unsigned long i;
wdenkaffae2b2002-08-17 09:36:01 +000094
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020095 printf("Call backtrace: ");
96 while (sp) {
97 if ((uint)sp > END_OF_MEM)
98 break;
wdenkaffae2b2002-08-17 09:36:01 +000099
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200100 i = sp[1];
101 if (cnt++ % 7 == 0)
102 printf("\n");
103 printf("%08lX ", i);
104 if (cnt > 32) break;
105 sp = (unsigned long *)*sp;
106 }
107 printf("\n");
wdenkaffae2b2002-08-17 09:36:01 +0000108}
109
110void show_regs(struct pt_regs * regs)
111{
112 int i;
113
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200114 printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
wdenkaffae2b2002-08-17 09:36:01 +0000115 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
116 printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
117 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
118 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
119 regs->msr&MSR_IR ? 1 : 0,
120 regs->msr&MSR_DR ? 1 : 0);
121
122 printf("\n");
123 for (i = 0; i < 32; i++) {
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200124 if ((i % 8) == 0) {
wdenkaffae2b2002-08-17 09:36:01 +0000125 printf("GPR%02d: ", i);
126 }
127
128 printf("%08lX ", regs->gpr[i]);
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200129 if ((i % 8) == 7) {
wdenkaffae2b2002-08-17 09:36:01 +0000130 printf("\n");
131 }
132 }
133}
134
135
136void
137_exception(int signr, struct pt_regs *regs)
138{
139 show_regs(regs);
140 print_backtrace((unsigned long *)regs->gpr[1]);
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200141 panic("Exception");
wdenkaffae2b2002-08-17 09:36:01 +0000142}
143
144void
145MachineCheckException(struct pt_regs *regs)
146{
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200147 unsigned long fixup, val;
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200148#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
149 u32 value2;
Stefan Roese27a528f2007-07-30 11:04:57 +0200150 int corr_ecc = 0;
151 int uncorr_ecc = 0;
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200152#endif
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200153
wdenkaffae2b2002-08-17 09:36:01 +0000154 if ((fixup = search_exception_table(regs->nip)) != 0) {
155 regs->nip = fixup;
Grzegorz Bernackic9240982007-07-31 18:51:48 +0200156 val = mfspr(MCSR);
157 /* Clear MCSR */
Stefan Roese9ca8d792007-08-02 08:33:56 +0200158 mtspr(SPRN_MCSR, val);
wdenkaffae2b2002-08-17 09:36:01 +0000159 return;
160 }
161
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500162#if defined(CONFIG_CMD_KGDB)
wdenkaffae2b2002-08-17 09:36:01 +0000163 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
164 return;
165#endif
166
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200167 printf("Machine Check Exception.\n");
wdenkaffae2b2002-08-17 09:36:01 +0000168 printf("Caused by (from msr): ");
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200169 printf("regs %p ", regs);
170
171 val = get_esr();
172
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700173#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200174 if (val& ESR_IMCP) {
175 printf("Instruction");
176 mtspr(ESR, val & ~ESR_IMCP);
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200177 } else {
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200178 printf("Data");
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200179 }
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200180 printf(" machine check.\n");
181
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700182#elif defined(CONFIG_440) || defined(CONFIG_405EX)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200183 if (val& ESR_IMCP){
184 printf("Instruction Synchronous Machine Check exception\n");
185 mtspr(SPRN_ESR, val & ~ESR_IMCP);
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200186 } else {
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200187 val = mfspr(MCSR);
188 if (val & MCSR_IB)
189 printf("Instruction Read PLB Error\n");
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700190#if defined(CONFIG_440)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200191 if (val & MCSR_DRB)
192 printf("Data Read PLB Error\n");
193 if (val & MCSR_DWB)
194 printf("Data Write PLB Error\n");
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700195#else
196 if (val & MCSR_DB)
197 printf("Data PLB Error\n");
198#endif
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200199 if (val & MCSR_TLBP)
200 printf("TLB Parity Error\n");
201 if (val & MCSR_ICP){
202 /*flush_instruction_cache(); */
203 printf("I-Cache Parity Error\n");
204 }
205 if (val & MCSR_DCSP)
206 printf("D-Cache Search Parity Error\n");
207 if (val & MCSR_DCFP)
208 printf("D-Cache Flush Parity Error\n");
209 if (val & MCSR_IMPE)
210 printf("Machine Check exception is imprecise\n");
211
212 /* Clear MCSR */
213 mtspr(SPRN_MCSR, val);
214 }
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200215#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
216 mfsdram(DDR0_00, val) ;
Stefan Roeseb0021442008-07-10 09:58:06 +0200217 printf("DDR0: DDR0_00 %lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200218 val = (val >> 16) & 0xff;
219 if (val & 0x80)
220 printf("DDR0: At least one interrupt active\n");
221 if (val & 0x40)
222 printf("DDR0: DRAM initialization complete.\n");
Stefan Roese27a528f2007-07-30 11:04:57 +0200223 if (val & 0x20) {
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200224 printf("DDR0: Multiple uncorrectable ECC events.\n");
Stefan Roese27a528f2007-07-30 11:04:57 +0200225 uncorr_ecc = 1;
226 }
227 if (val & 0x10) {
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200228 printf("DDR0: Single uncorrectable ECC event.\n");
Stefan Roese27a528f2007-07-30 11:04:57 +0200229 uncorr_ecc = 1;
230 }
231 if (val & 0x08) {
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200232 printf("DDR0: Multiple correctable ECC events.\n");
Stefan Roese27a528f2007-07-30 11:04:57 +0200233 corr_ecc = 1;
234 }
235 if (val & 0x04) {
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200236 printf("DDR0: Single correctable ECC event.\n");
Stefan Roese27a528f2007-07-30 11:04:57 +0200237 corr_ecc = 1;
238 }
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200239 if (val & 0x02)
240 printf("Multiple accesses outside the defined"
241 " physical memory space detected\n");
242 if (val & 0x01)
243 printf("DDR0: Single access outside the defined"
244 " physical memory space detected.\n");
245
246 mfsdram(DDR0_01, val);
247 val = (val >> 8) & 0x7;
248 switch (val ) {
249 case 0:
250 printf("DDR0: Write Out-of-Range command\n");
251 break;
252 case 1:
253 printf("DDR0: Read Out-of-Range command\n");
254 break;
255 case 2:
256 printf("DDR0: Masked write Out-of-Range command\n");
257 break;
258 case 4:
259 printf("DDR0: Wrap write Out-of-Range command\n");
260 break;
261 case 5:
262 printf("DDR0: Wrap read Out-of-Range command\n");
263 break;
264 default:
265 mfsdram(DDR0_01, value2);
Stefan Roeseb0021442008-07-10 09:58:06 +0200266 printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200267 }
268 mfsdram(DDR0_23, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200269 if (((val >> 16) & 0xff) && corr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200270 printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200271 (val >> 16) & 0xff);
272 mfsdram(DDR0_23, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200273 if (((val >> 8) & 0xff) && uncorr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200274 printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200275 (val >> 8) & 0xff);
276 mfsdram(DDR0_33, val);
277 if (val)
278 printf("DDR0: Address of command that caused an "
Stefan Roeseb0021442008-07-10 09:58:06 +0200279 "Out-of-Range interrupt %lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200280 mfsdram(DDR0_34, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200281 if (val && uncorr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200282 printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200283 mfsdram(DDR0_35, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200284 if (val && uncorr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200285 printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200286 mfsdram(DDR0_36, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200287 if (val && uncorr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200288 printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200289 mfsdram(DDR0_37, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200290 if (val && uncorr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200291 printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200292 mfsdram(DDR0_38, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200293 if (val && corr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200294 printf("DDR0: Address of correctable ECC event %lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200295 mfsdram(DDR0_39, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200296 if (val && corr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200297 printf("DDR0: Address of correctable ECC event %lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200298 mfsdram(DDR0_40, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200299 if (val && corr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200300 printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200301 mfsdram(DDR0_41, val);
Stefan Roese27a528f2007-07-30 11:04:57 +0200302 if (val && corr_ecc)
Stefan Roeseb0021442008-07-10 09:58:06 +0200303 printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
Niklaus Gigera1bd6202007-06-25 17:03:13 +0200304#endif /* CONFIG_440EPX */
305#endif /* CONFIG_440 */
wdenkaffae2b2002-08-17 09:36:01 +0000306 show_regs(regs);
307 print_backtrace((unsigned long *)regs->gpr[1]);
308 panic("machine check");
309}
310
311void
312AlignmentException(struct pt_regs *regs)
313{
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500314#if defined(CONFIG_CMD_KGDB)
wdenkaffae2b2002-08-17 09:36:01 +0000315 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
316 return;
317#endif
318
319 show_regs(regs);
320 print_backtrace((unsigned long *)regs->gpr[1]);
321 panic("Alignment Exception");
322}
323
324void
325ProgramCheckException(struct pt_regs *regs)
326{
wdenk8bde7f72003-06-27 21:31:46 +0000327 long esr_val;
wdenkaffae2b2002-08-17 09:36:01 +0000328
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500329#if defined(CONFIG_CMD_KGDB)
wdenkaffae2b2002-08-17 09:36:01 +0000330 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
331 return;
332#endif
333
334 show_regs(regs);
335
wdenk8bde7f72003-06-27 21:31:46 +0000336 esr_val = get_esr();
337 if( esr_val & ESR_PIL )
wdenkaffae2b2002-08-17 09:36:01 +0000338 printf( "** Illegal Instruction **\n" );
wdenk8bde7f72003-06-27 21:31:46 +0000339 else if( esr_val & ESR_PPR )
wdenkaffae2b2002-08-17 09:36:01 +0000340 printf( "** Privileged Instruction **\n" );
wdenk8bde7f72003-06-27 21:31:46 +0000341 else if( esr_val & ESR_PTR )
wdenkaffae2b2002-08-17 09:36:01 +0000342 printf( "** Trap Instruction **\n" );
343
344 print_backtrace((unsigned long *)regs->gpr[1]);
345 panic("Program Check Exception");
346}
347
348void
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200349DecrementerPITException(struct pt_regs *regs)
wdenkaffae2b2002-08-17 09:36:01 +0000350{
wdenk8bde7f72003-06-27 21:31:46 +0000351 /*
352 * Reset PIT interrupt
353 */
354 set_tsr(0x08000000);
wdenkaffae2b2002-08-17 09:36:01 +0000355
wdenk8bde7f72003-06-27 21:31:46 +0000356 /*
357 * Call timer_interrupt routine in interrupts.c
358 */
359 timer_interrupt(NULL);
wdenkaffae2b2002-08-17 09:36:01 +0000360}
361
362
363void
364UnknownException(struct pt_regs *regs)
365{
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500366#if defined(CONFIG_CMD_KGDB)
wdenkaffae2b2002-08-17 09:36:01 +0000367 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
368 return;
369#endif
370
371 printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
372 regs->nip, regs->msr, regs->trap);
373 _exception(0, regs);
374}
375
376void
377DebugException(struct pt_regs *regs)
378{
379 printf("Debugger trap at @ %lx\n", regs->nip );
380 show_regs(regs);
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500381#if defined(CONFIG_CMD_BEDBUG)
wdenkaffae2b2002-08-17 09:36:01 +0000382 do_bedbug_breakpoint( regs );
383#endif
384}
385
386/* Probe an address by reading. If not present, return -1, otherwise
387 * return 0.
388 */
389int
390addr_probe(uint *addr)
391{
392#if 0
393 int retval;
394
395 __asm__ __volatile__( \
396 "1: lwz %0,0(%1)\n" \
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200397 " eieio\n" \
398 " li %0,0\n" \
399 "2:\n" \
400 ".section .fixup,\"ax\"\n" \
401 "3: li %0,-1\n" \
402 " b 2b\n" \
403 ".section __ex_table,\"a\"\n" \
404 " .align 2\n" \
405 " .long 1b,3b\n" \
406 ".text" \
407 : "=r" (retval) : "r"(addr));
wdenkaffae2b2002-08-17 09:36:01 +0000408
409 return (retval);
410#endif
411 return 0;
412}