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York Sun7288c2c2015-03-20 19:28:23 -07001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
10#include "ddr.h"
11
12DECLARE_GLOBAL_DATA_PTR;
13
14void fsl_ddr_board_options(memctl_options_t *popts,
15 dimm_params_t *pdimm,
16 unsigned int ctrl_num)
17{
18 u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
19 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
20 ulong ddr_freq;
21 int slot;
22
23 if (ctrl_num > 2) {
24 printf("Not supported controller number %d\n", ctrl_num);
25 return;
26 }
27
28 for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
29 if (pdimm[slot].n_ranks)
30 break;
31 }
32
33 if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
34 return;
35
36 /*
37 * we use identical timing for all slots. If needed, change the code
38 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
39 */
40 if (popts->registered_dimm_en)
41 pbsp = rdimms[ctrl_num];
42 else
43 pbsp = udimms[ctrl_num];
44
45
46 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
47 * freqency and n_banks specified in board_specific_parameters table.
48 */
49 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
50 while (pbsp->datarate_mhz_high) {
51 if (pbsp->n_ranks == pdimm[slot].n_ranks &&
52 (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
53 if (ddr_freq <= pbsp->datarate_mhz_high) {
54 popts->clk_adjust = pbsp->clk_adjust;
55 popts->wrlvl_start = pbsp->wrlvl_start;
56 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
57 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
58 goto found;
59 }
60 pbsp_highest = pbsp;
61 }
62 pbsp++;
63 }
64
65 if (pbsp_highest) {
66 printf("Error: board specific timing not found for data rate %lu MT/s\n"
67 "Trying to use the highest speed (%u) parameters\n",
68 ddr_freq, pbsp_highest->datarate_mhz_high);
69 popts->clk_adjust = pbsp_highest->clk_adjust;
70 popts->wrlvl_start = pbsp_highest->wrlvl_start;
71 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
72 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
73 } else {
74 panic("DIMM is not supported by this board");
75 }
76found:
77 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
78 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
79 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
80 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
81 pbsp->wrlvl_ctl_3);
82
83 if (ctrl_num == CONFIG_DP_DDR_CTRL) {
84 /* force DDR bus width to 32 bits */
85 popts->data_bus_width = 1;
86 popts->otf_burst_chop_en = 0;
87 popts->burst_length = DDR_BL8;
88 popts->bstopre = 0; /* enable auto precharge */
89 /*
90 * Layout optimization results byte mapping
91 * Byte 0 -> Byte ECC
92 * Byte 1 -> Byte 3
93 * Byte 2 -> Byte 2
94 * Byte 3 -> Byte 1
95 * Byte ECC -> Byte 0
96 */
97 dq_mapping_0 = pdimm[slot].dq_mapping[0];
98 dq_mapping_2 = pdimm[slot].dq_mapping[2];
99 dq_mapping_3 = pdimm[slot].dq_mapping[3];
100 pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
101 pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
102 pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
103 pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
104 pdimm[slot].dq_mapping[6] = dq_mapping_2;
105 pdimm[slot].dq_mapping[7] = dq_mapping_3;
106 pdimm[slot].dq_mapping[8] = dq_mapping_0;
107 pdimm[slot].dq_mapping[9] = 0;
108 pdimm[slot].dq_mapping[10] = 0;
109 pdimm[slot].dq_mapping[11] = 0;
110 pdimm[slot].dq_mapping[12] = 0;
111 pdimm[slot].dq_mapping[13] = 0;
112 pdimm[slot].dq_mapping[14] = 0;
113 pdimm[slot].dq_mapping[15] = 0;
114 pdimm[slot].dq_mapping[16] = 0;
115 pdimm[slot].dq_mapping[17] = 0;
116 }
117 /* To work at higher than 1333MT/s */
118 popts->half_strength_driver_enable = 0;
119 /*
120 * Write leveling override
121 */
122 popts->wrlvl_override = 1;
123 popts->wrlvl_sample = 0x0; /* 32 clocks */
124
125 /*
126 * Rtt and Rtt_WR override
127 */
128 popts->rtt_override = 0;
129
130 /* Enable ZQ calibration */
131 popts->zq_en = 1;
132
133 if (ddr_freq < 2350) {
134 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
135 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
136 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
137 DDR_CDR2_VREF_RANGE_2;
138 } else {
139 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
140 DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
141 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
142 DDR_CDR2_VREF_RANGE_2;
143 }
144}
145
146phys_size_t initdram(int board_type)
147{
148 phys_size_t dram_size;
149
Scott Woodb2d5ac52015-03-24 13:25:02 -0700150#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
151 return fsl_ddr_sdram_size();
152#else
York Sun7288c2c2015-03-20 19:28:23 -0700153 puts("Initializing DDR....using SPD\n");
154
155 dram_size = fsl_ddr_sdram();
Scott Woodb2d5ac52015-03-24 13:25:02 -0700156#endif
York Sun7288c2c2015-03-20 19:28:23 -0700157
158 return dram_size;
159}
160
161void dram_init_banksize(void)
162{
163#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
164 phys_size_t dp_ddr_size;
165#endif
166
167 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
168 if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
169 gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
170 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
171 gd->bd->bi_dram[1].size = gd->ram_size -
172 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
173 } else {
174 gd->bd->bi_dram[0].size = gd->ram_size;
175 }
176
177#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
178 /* initialize DP-DDR here */
179 puts("DP-DDR: ");
180 /*
181 * DDR controller use 0 as the base address for binding.
182 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
183 */
184 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
185 CONFIG_DP_DDR_CTRL,
186 CONFIG_DP_DDR_NUM_CTRLS,
187 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
188 NULL, NULL, NULL);
189 if (dp_ddr_size) {
190 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
191 gd->bd->bi_dram[2].size = dp_ddr_size;
192 } else {
193 puts("Not detected");
194 }
195#endif
196}