blob: 524975183043c84ffa9295c83f589054761b8141 [file] [log] [blame]
York Sunb5b06fb2012-12-23 19:25:27 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunb5b06fb2012-12-23 19:25:27 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
York Sun15672c62014-04-30 14:43:49 -070010#define CONFIG_DISPLAY_BOARDINFO
11
York Sunb5b06fb2012-12-23 19:25:27 +000012/*
13 * B4860 QDS board configuration file
14 */
15#define CONFIG_B4860QDS
16#define CONFIG_PHYS_64BIT
17
18#ifdef CONFIG_RAMBOOT_PBL
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053019#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
20#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
21#ifndef CONFIG_NAND
York Sunb5b06fb2012-12-23 19:25:27 +000022#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053024#else
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053025#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
26#define CONFIG_SPL_ENV_SUPPORT
27#define CONFIG_SPL_SERIAL_SUPPORT
28#define CONFIG_SPL_FLUSH_IMAGE
29#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
30#define CONFIG_SPL_LIBGENERIC_SUPPORT
31#define CONFIG_SPL_LIBCOMMON_SUPPORT
32#define CONFIG_SPL_I2C_SUPPORT
33#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
34#define CONFIG_FSL_LAW /* Use common FSL init code */
35#define CONFIG_SYS_TEXT_BASE 0x00201000
36#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
37#define CONFIG_SPL_PAD_TO 0x40000
38#define CONFIG_SPL_MAX_SIZE 0x28000
39#define RESET_VECTOR_OFFSET 0x27FFC
40#define BOOT_PAGE_OFFSET 0x27000
41#define CONFIG_SPL_NAND_SUPPORT
42#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
43#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
44#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
45#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
46#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
47#define CONFIG_SPL_NAND_BOOT
48#ifdef CONFIG_SPL_BUILD
49#define CONFIG_SPL_SKIP_RELOCATE
50#define CONFIG_SPL_COMMON_INIT_DDR
51#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
52#define CONFIG_SYS_NO_FLASH
53#endif
54#endif
York Sunb5b06fb2012-12-23 19:25:27 +000055#endif
56
Liu Gang5870fe42013-05-07 16:30:48 +080057#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
58/* Set 1M boot space */
59#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
60#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
61 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
62#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
63#define CONFIG_SYS_NO_FLASH
64#endif
65
York Sunb5b06fb2012-12-23 19:25:27 +000066/* High Level Configuration Options */
67#define CONFIG_BOOKE
York Sunb5b06fb2012-12-23 19:25:27 +000068#define CONFIG_E500 /* BOOKE e500 family */
69#define CONFIG_E500MC /* BOOKE e500mc family */
70#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
York Sunb5b06fb2012-12-23 19:25:27 +000071#define CONFIG_MP /* support multiple processors */
72
73#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053074#define CONFIG_SYS_TEXT_BASE 0xeff40000
York Sunb5b06fb2012-12-23 19:25:27 +000075#endif
76
77#ifndef CONFIG_RESET_VECTOR_ADDRESS
78#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
79#endif
80
81#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
82#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
83#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053084#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
York Sunb5b06fb2012-12-23 19:25:27 +000085#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040086#define CONFIG_PCIE1 /* PCIE controller 1 */
York Sunb5b06fb2012-12-23 19:25:27 +000087#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
88#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
89
90#ifndef CONFIG_PPC_B4420
91#define CONFIG_SYS_SRIO
92#define CONFIG_SRIO1 /* SRIO port 1 */
93#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang3a017992013-05-07 16:30:47 +080094#define CONFIG_SRIO_PCIE_BOOT_MASTER
York Sunb5b06fb2012-12-23 19:25:27 +000095#endif
96
97#define CONFIG_FSL_LAW /* Use common FSL init code */
98
99/* I2C bus multiplexer */
100#define I2C_MUX_PCA_ADDR 0x77
101
102/* VSC Crossbar switches */
103#define CONFIG_VSC_CROSSBAR
104#define I2C_CH_DEFAULT 0x8
105#define I2C_CH_VSC3316 0xc
106#define I2C_CH_VSC3308 0xd
107
108#define VSC3316_TX_ADDRESS 0x70
109#define VSC3316_RX_ADDRESS 0x71
110#define VSC3308_TX_ADDRESS 0x02
111#define VSC3308_RX_ADDRESS 0x03
112
Shaveta Leekhacb033742013-07-02 14:43:53 +0530113/* IDT clock synthesizers */
114#define CONFIG_IDT8T49N222A
115#define I2C_CH_IDT 0x9
116
117#define IDT_SERDES1_ADDRESS 0x6E
118#define IDT_SERDES2_ADDRESS 0x6C
119
Shaveta Leekha652e29b2014-04-11 14:12:40 +0530120/* Voltage monitor on channel 2*/
121#define I2C_MUX_CH_VOL_MONITOR 0xa
122#define I2C_VOL_MONITOR_ADDR 0x40
123#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
124#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
125#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
126
127#define CONFIG_ZM7300
128#define I2C_MUX_CH_DPM 0xa
129#define I2C_DPM_ADDR 0x28
130
York Sunb5b06fb2012-12-23 19:25:27 +0000131#define CONFIG_ENV_OVERWRITE
132
133#ifdef CONFIG_SYS_NO_FLASH
Liu Gang5870fe42013-05-07 16:30:48 +0800134#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
York Sunb5b06fb2012-12-23 19:25:27 +0000135#define CONFIG_ENV_IS_NOWHERE
Liu Gang5870fe42013-05-07 16:30:48 +0800136#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000137#else
138#define CONFIG_FLASH_CFI_DRIVER
139#define CONFIG_SYS_FLASH_CFI
140#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
141#endif
142
York Sunb5b06fb2012-12-23 19:25:27 +0000143#if defined(CONFIG_SPIFLASH)
144#define CONFIG_SYS_EXTRA_ENV_RELOC
145#define CONFIG_ENV_IS_IN_SPI_FLASH
146#define CONFIG_ENV_SPI_BUS 0
147#define CONFIG_ENV_SPI_CS 0
148#define CONFIG_ENV_SPI_MAX_HZ 10000000
149#define CONFIG_ENV_SPI_MODE 0
150#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
151#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
152#define CONFIG_ENV_SECT_SIZE 0x10000
153#elif defined(CONFIG_SDCARD)
154#define CONFIG_SYS_EXTRA_ENV_RELOC
155#define CONFIG_ENV_IS_IN_MMC
156#define CONFIG_SYS_MMC_ENV_DEV 0
157#define CONFIG_ENV_SIZE 0x2000
158#define CONFIG_ENV_OFFSET (512 * 1097)
159#elif defined(CONFIG_NAND)
160#define CONFIG_SYS_EXTRA_ENV_RELOC
161#define CONFIG_ENV_IS_IN_NAND
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530162#define CONFIG_ENV_SIZE 0x2000
163#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800164#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
165#define CONFIG_ENV_IS_IN_REMOTE
166#define CONFIG_ENV_ADDR 0xffe20000
167#define CONFIG_ENV_SIZE 0x2000
168#elif defined(CONFIG_ENV_IS_NOWHERE)
169#define CONFIG_ENV_SIZE 0x2000
York Sunb5b06fb2012-12-23 19:25:27 +0000170#else
171#define CONFIG_ENV_IS_IN_FLASH
172#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
173#define CONFIG_ENV_SIZE 0x2000
174#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
175#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000176
177#ifndef __ASSEMBLY__
178unsigned long get_board_sys_clk(void);
179unsigned long get_board_ddr_clk(void);
180#endif
181#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
182#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
183
184/*
185 * These can be toggled for performance analysis, otherwise use default.
186 */
187#define CONFIG_SYS_CACHE_STASHING
188#define CONFIG_BTB /* toggle branch predition */
189#define CONFIG_DDR_ECC
190#ifdef CONFIG_DDR_ECC
191#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
192#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
193#endif
194
195#define CONFIG_ENABLE_36BIT_PHYS
196
197#ifdef CONFIG_PHYS_64BIT
198#define CONFIG_ADDR_MAP
199#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
200#endif
201
202#if 0
203#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
204#endif
205#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
206#define CONFIG_SYS_MEMTEST_END 0x00400000
207#define CONFIG_SYS_ALT_MEMTEST
208#define CONFIG_PANIC_HANG /* do not reset board on panic */
209
210/*
211 * Config the L3 Cache as L3 SRAM
212 */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530213#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
214#define CONFIG_SYS_L3_SIZE 256 << 10
215#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
216#ifdef CONFIG_NAND
217#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
218#endif
219#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
220#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
221#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
222#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
York Sunb5b06fb2012-12-23 19:25:27 +0000223
224#ifdef CONFIG_PHYS_64BIT
225#define CONFIG_SYS_DCSRBAR 0xf0000000
226#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
227#endif
228
229/* EEPROM */
Shaveta Leekha1de271b2014-09-04 16:17:09 +0530230#define CONFIG_ID_EEPROM
York Sunb5b06fb2012-12-23 19:25:27 +0000231#define CONFIG_SYS_I2C_EEPROM_NXID
232#define CONFIG_SYS_EEPROM_BUS_NUM 0
233#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
234#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
237
238/*
239 * DDR Setup
240 */
241#define CONFIG_VERY_BIG_RAM
242#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
243#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
244
245/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
246#define CONFIG_DIMM_SLOTS_PER_CTLR 1
247#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
248
249#define CONFIG_DDR_SPD
250#define CONFIG_SYS_DDR_RAW_TIMING
York Sun5614e712013-09-30 09:22:09 -0700251#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530252#ifndef CONFIG_SPL_BUILD
York Sunb5b06fb2012-12-23 19:25:27 +0000253#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530254#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000255
256#define CONFIG_SYS_SPD_BUS_NUM 0
257#define SPD_EEPROM_ADDRESS1 0x51
258#define SPD_EEPROM_ADDRESS2 0x53
259
260#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
261#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
262
263/*
264 * IFC Definitions
265 */
266#define CONFIG_SYS_FLASH_BASE 0xe0000000
267#ifdef CONFIG_PHYS_64BIT
268#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
269#else
270#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
271#endif
272
273#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
274#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
275 + 0x8000000) | \
276 CSPR_PORT_SIZE_16 | \
277 CSPR_MSEL_NOR | \
278 CSPR_V)
279#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
280#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
281 CSPR_PORT_SIZE_16 | \
282 CSPR_MSEL_NOR | \
283 CSPR_V)
284#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
285/* NOR Flash Timing Params */
286#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
287#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
Prabhakar Kushwaha4d0e6e02013-05-17 13:40:52 +0530288 FTIM0_NOR_TEADC(0x04) | \
York Sunb5b06fb2012-12-23 19:25:27 +0000289 FTIM0_NOR_TEAHC(0x20))
290#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
291 FTIM1_NOR_TRAD_NOR(0x1A) |\
292 FTIM1_NOR_TSEQRAD_NOR(0x13))
293#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
294 FTIM2_NOR_TCH(0x0E) | \
295 FTIM2_NOR_TWPH(0x0E) | \
296 FTIM2_NOR_TWP(0x1c))
297#define CONFIG_SYS_NOR_FTIM3 0x0
298
299#define CONFIG_SYS_FLASH_QUIET_TEST
300#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
301
302#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
303#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
304#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
305#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
306
307#define CONFIG_SYS_FLASH_EMPTY_INFO
308#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
309 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
310
311#define CONFIG_FSL_QIXIS /* use common QIXIS code */
312#define CONFIG_FSL_QIXIS_V2
313#define QIXIS_BASE 0xffdf0000
314#ifdef CONFIG_PHYS_64BIT
315#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
316#else
317#define QIXIS_BASE_PHYS QIXIS_BASE
318#endif
319#define QIXIS_LBMAP_SWITCH 0x01
320#define QIXIS_LBMAP_MASK 0x0f
321#define QIXIS_LBMAP_SHIFT 0
322#define QIXIS_LBMAP_DFLTBANK 0x00
323#define QIXIS_LBMAP_ALTBANK 0x02
324#define QIXIS_RST_CTL_RESET 0x31
325#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
326#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
327#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
328
329#define CONFIG_SYS_CSPR3_EXT (0xf)
330#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
331 | CSPR_PORT_SIZE_8 \
332 | CSPR_MSEL_GPCM \
333 | CSPR_V)
334#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
335#define CONFIG_SYS_CSOR3 0x0
336/* QIXIS Timing parameters for IFC CS3 */
337#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
338 FTIM0_GPCM_TEADC(0x0e) | \
339 FTIM0_GPCM_TEAHC(0x0e))
340#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
341 FTIM1_GPCM_TRAD(0x1f))
342#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800343 FTIM2_GPCM_TCH(0x8) | \
York Sunb5b06fb2012-12-23 19:25:27 +0000344 FTIM2_GPCM_TWP(0x1f))
345#define CONFIG_SYS_CS3_FTIM3 0x0
346
347/* NAND Flash on IFC */
348#define CONFIG_NAND_FSL_IFC
York Sunab13ad52013-12-17 11:21:09 -0800349#define CONFIG_SYS_NAND_MAX_ECCPOS 256
350#define CONFIG_SYS_NAND_MAX_OOBFREE 2
York Sunb5b06fb2012-12-23 19:25:27 +0000351#define CONFIG_SYS_NAND_BASE 0xff800000
352#ifdef CONFIG_PHYS_64BIT
353#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
354#else
355#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
356#endif
357
358#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
359#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
360 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
361 | CSPR_MSEL_NAND /* MSEL = NAND */ \
362 | CSPR_V)
363#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
364
365#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
366 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
367 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
368 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
369 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
370 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
371 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
372
373#define CONFIG_SYS_NAND_ONFI_DETECTION
374
375/* ONFI NAND Flash mode0 Timing Params */
376#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
377 FTIM0_NAND_TWP(0x18) | \
378 FTIM0_NAND_TWCHT(0x07) | \
379 FTIM0_NAND_TWH(0x0a))
380#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
381 FTIM1_NAND_TWBE(0x39) | \
382 FTIM1_NAND_TRR(0x0e) | \
383 FTIM1_NAND_TRP(0x18))
384#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
385 FTIM2_NAND_TREH(0x0a) | \
386 FTIM2_NAND_TWHRE(0x1e))
387#define CONFIG_SYS_NAND_FTIM3 0x0
388
389#define CONFIG_SYS_NAND_DDR_LAW 11
390
391#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
392#define CONFIG_SYS_MAX_NAND_DEVICE 1
York Sunb5b06fb2012-12-23 19:25:27 +0000393#define CONFIG_CMD_NAND
394
395#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
396
397#if defined(CONFIG_NAND)
398#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
399#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
400#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
401#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
402#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
403#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
404#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
405#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
406#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
407#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
408#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
409#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
410#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
411#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
412#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
413#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
414#else
415#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
416#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
417#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
418#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
419#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
420#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
421#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
422#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
423#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
424#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
425#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
426#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
427#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
428#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
429#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
430#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
431#endif
432#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
433#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
434#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
435#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
436#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
437#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
438#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
439#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
440
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530441#ifdef CONFIG_SPL_BUILD
442#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
443#else
444#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
445#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000446
447#if defined(CONFIG_RAMBOOT_PBL)
448#define CONFIG_SYS_RAMBOOT
449#endif
450
451#define CONFIG_BOARD_EARLY_INIT_R
452#define CONFIG_MISC_INIT_R
453
454#define CONFIG_HWCONFIG
455
456/* define to use L1 as initial stack */
457#define CONFIG_L1_INIT_RAM
458#define CONFIG_SYS_INIT_RAM_LOCK
459#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
460#ifdef CONFIG_PHYS_64BIT
461#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700462#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
York Sunb5b06fb2012-12-23 19:25:27 +0000463/* The assembler doesn't like typecast */
464#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
465 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
466 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
467#else
York Sunb3142e22015-08-17 13:31:51 -0700468#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
York Sunb5b06fb2012-12-23 19:25:27 +0000469#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
470#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
471#endif
472#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
473
474#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
475 GENERATED_GBL_DATA_SIZE)
476#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
477
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530478#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
York Sunb5b06fb2012-12-23 19:25:27 +0000479#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
480
481/* Serial Port - controlled on board with jumper J8
482 * open - index 2
483 * shorted - index 1
484 */
485#define CONFIG_CONS_INDEX 1
York Sunb5b06fb2012-12-23 19:25:27 +0000486#define CONFIG_SYS_NS16550_SERIAL
487#define CONFIG_SYS_NS16550_REG_SIZE 1
488#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
489
490#define CONFIG_SYS_BAUDRATE_TABLE \
491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
492
493#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
494#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
495#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
496#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530497#ifndef CONFIG_SPL_BUILD
York Sunb5b06fb2012-12-23 19:25:27 +0000498#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530499#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000500
York Sunb5b06fb2012-12-23 19:25:27 +0000501/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200502#define CONFIG_SYS_I2C
503#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
504#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
505#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
506#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
507#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
508#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
509#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
York Sunb5b06fb2012-12-23 19:25:27 +0000510
511/*
512 * RTC configuration
513 */
514#define RTC
515#define CONFIG_RTC_DS3231 1
516#define CONFIG_SYS_I2C_RTC_ADDR 0x68
517
518/*
519 * RapidIO
520 */
521#ifdef CONFIG_SYS_SRIO
522#ifdef CONFIG_SRIO1
523#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
524#ifdef CONFIG_PHYS_64BIT
525#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
526#else
527#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
528#endif
529#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
530#endif
531
532#ifdef CONFIG_SRIO2
533#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
534#ifdef CONFIG_PHYS_64BIT
535#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
536#else
537#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
538#endif
539#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
540#endif
541#endif
542
543/*
544 * for slave u-boot IMAGE instored in master memory space,
545 * PHYS must be aligned based on the SIZE
546 */
Liu Gange4911812014-05-15 14:30:34 +0800547#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
548#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
549#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
550#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
York Sunb5b06fb2012-12-23 19:25:27 +0000551/*
552 * for slave UCODE and ENV instored in master memory space,
553 * PHYS must be aligned based on the SIZE
554 */
Liu Gange4911812014-05-15 14:30:34 +0800555#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
York Sunb5b06fb2012-12-23 19:25:27 +0000556#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
557#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
558
559/* slave core release by master*/
560#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
561#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
562
563/*
564 * SRIO_PCIE_BOOT - SLAVE
565 */
566#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
567#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
568#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
569 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
570#endif
571
572/*
573 * eSPI - Enhanced SPI
574 */
York Sunb5b06fb2012-12-23 19:25:27 +0000575#define CONFIG_SF_DEFAULT_SPEED 10000000
576#define CONFIG_SF_DEFAULT_MODE 0
577
578/*
Shaveta Leekha6eaeba22013-03-25 07:40:24 +0000579 * MAPLE
580 */
581#ifdef CONFIG_PHYS_64BIT
582#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
583#else
584#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
585#endif
586
587/*
York Sunb5b06fb2012-12-23 19:25:27 +0000588 * General PCI
589 * Memory space is mapped 1-1, but I/O space must start from 0.
590 */
591
592/* controller 1, direct to uli, tgtid 3, Base address 20000 */
593#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
594#ifdef CONFIG_PHYS_64BIT
595#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
596#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
597#else
598#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
599#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
600#endif
601#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
602#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
603#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
604#ifdef CONFIG_PHYS_64BIT
605#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
606#else
607#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
608#endif
609#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
610
611/* Qman/Bman */
612#ifndef CONFIG_NOBQFMAN
613#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
614#define CONFIG_SYS_BMAN_NUM_PORTALS 25
615#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
616#ifdef CONFIG_PHYS_64BIT
617#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
618#else
619#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
620#endif
621#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500622#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
623#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
624#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
625#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
626#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
627 CONFIG_SYS_BMAN_CENA_SIZE)
628#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
629#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
York Sunb5b06fb2012-12-23 19:25:27 +0000630#define CONFIG_SYS_QMAN_NUM_PORTALS 25
631#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
632#ifdef CONFIG_PHYS_64BIT
633#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
634#else
635#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
636#endif
637#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500638#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
639#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
640#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
641#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
642#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
643 CONFIG_SYS_QMAN_CENA_SIZE)
644#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
645#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
York Sunb5b06fb2012-12-23 19:25:27 +0000646
647#define CONFIG_SYS_DPAA_FMAN
648
Minghuan Lian0795eff2013-07-03 18:32:41 +0800649#define CONFIG_SYS_DPAA_RMAN
650
York Sunb5b06fb2012-12-23 19:25:27 +0000651/* Default address of microcode for the Linux Fman driver */
652#if defined(CONFIG_SPIFLASH)
653/*
654 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
655 * env, so we got 0x110000.
656 */
657#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800658#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
York Sunb5b06fb2012-12-23 19:25:27 +0000659#elif defined(CONFIG_SDCARD)
660/*
661 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
662 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
663 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
664 */
665#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800666#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
York Sunb5b06fb2012-12-23 19:25:27 +0000667#elif defined(CONFIG_NAND)
668#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530669#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800670#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
671/*
672 * Slave has no ucode locally, it can fetch this from remote. When implementing
673 * in two corenet boards, slave's ucode could be stored in master's memory
674 * space, the address can be mapped from slave TLB->slave LAW->
675 * slave SRIO or PCIE outbound window->master inbound window->
676 * master LAW->the ucode address in master's memory space.
677 */
678#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800679#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
York Sunb5b06fb2012-12-23 19:25:27 +0000680#else
681#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800682#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
York Sunb5b06fb2012-12-23 19:25:27 +0000683#endif
684#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
685#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
686#endif /* CONFIG_NOBQFMAN */
687
688#ifdef CONFIG_SYS_DPAA_FMAN
689#define CONFIG_FMAN_ENET
690#define CONFIG_PHYLIB_10G
691#define CONFIG_PHY_VITESSE
692#define CONFIG_PHY_TERANETICS
693#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
694#define SGMII_CARD_PORT2_PHY_ADDR 0x10
695#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
696#define SGMII_CARD_PORT4_PHY_ADDR 0x11
697#endif
698
699#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000700#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunb5b06fb2012-12-23 19:25:27 +0000701#define CONFIG_PCI_PNP /* do pci plug-and-play */
York Sunb5b06fb2012-12-23 19:25:27 +0000702
703#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
704#define CONFIG_DOS_PARTITION
705#endif /* CONFIG_PCI */
706
707#ifdef CONFIG_FMAN_ENET
Shaveta Leekhaf1d80742014-11-12 16:00:22 +0530708#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
709#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
Suresh Gupta16d88f42013-03-25 07:40:13 +0000710
711/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
712#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
713#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
714
York Sunb5b06fb2012-12-23 19:25:27 +0000715#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
716#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
717#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
718#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
719
720#define CONFIG_MII /* MII PHY management */
721#define CONFIG_ETHPRIME "FM1@DTSEC1"
722#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
723#endif
724
Shaohui Xieb24f6d42014-11-13 11:27:49 +0800725#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
726
York Sunb5b06fb2012-12-23 19:25:27 +0000727/*
728 * Environment
729 */
730#define CONFIG_LOADS_ECHO /* echo on for serial download */
731#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
732
733/*
734 * Command line configuration.
735 */
York Sunb5b06fb2012-12-23 19:25:27 +0000736#define CONFIG_CMD_DATE
York Sunb5b06fb2012-12-23 19:25:27 +0000737#define CONFIG_CMD_EEPROM
York Sunb5b06fb2012-12-23 19:25:27 +0000738#define CONFIG_CMD_ERRATA
York Sunb5b06fb2012-12-23 19:25:27 +0000739#define CONFIG_CMD_IRQ
York Sunb5b06fb2012-12-23 19:25:27 +0000740#define CONFIG_CMD_REGINFO
York Sunb5b06fb2012-12-23 19:25:27 +0000741
742#ifdef CONFIG_PCI
743#define CONFIG_CMD_PCI
York Sunb5b06fb2012-12-23 19:25:27 +0000744#endif
745
Ruchika Gupta737537e2014-10-15 11:35:31 +0530746/* Hash command with SHA acceleration supported in hardware */
747#ifdef CONFIG_FSL_CAAM
748#define CONFIG_CMD_HASH
749#define CONFIG_SHA_HW_ACCEL
750#endif
751
York Sunb5b06fb2012-12-23 19:25:27 +0000752/*
753* USB
754*/
755#define CONFIG_HAS_FSL_DR_USB
756
757#ifdef CONFIG_HAS_FSL_DR_USB
758#define CONFIG_USB_EHCI
759
760#ifdef CONFIG_USB_EHCI
York Sunb5b06fb2012-12-23 19:25:27 +0000761#define CONFIG_USB_STORAGE
762#define CONFIG_USB_EHCI_FSL
763#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
York Sunb5b06fb2012-12-23 19:25:27 +0000764#endif
765#endif
766
767/*
768 * Miscellaneous configurable options
769 */
770#define CONFIG_SYS_LONGHELP /* undef to save memory */
771#define CONFIG_CMDLINE_EDITING /* Command-line editing */
772#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
773#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sunb5b06fb2012-12-23 19:25:27 +0000774#ifdef CONFIG_CMD_KGDB
775#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
776#else
777#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
778#endif
779#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
780#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
781#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sunb5b06fb2012-12-23 19:25:27 +0000782
783/*
784 * For booting Linux, the board info and command line data
785 * have to be in the first 64 MB of memory, since this is
786 * the maximum mapped by the Linux kernel during initialization.
787 */
788#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
789#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
790
791#ifdef CONFIG_CMD_KGDB
792#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
York Sunb5b06fb2012-12-23 19:25:27 +0000793#endif
794
795/*
796 * Environment Configuration
797 */
798#define CONFIG_ROOTPATH "/opt/nfsroot"
799#define CONFIG_BOOTFILE "uImage"
800#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
801
802/* default location for tftp and bootm */
803#define CONFIG_LOADADDR 1000000
804
805#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
806
807#define CONFIG_BAUDRATE 115200
808
809#define __USB_PHY_TYPE ulpi
810
Shaveta Leekha38e0e152014-09-04 11:43:57 +0530811#ifdef CONFIG_PPC_B4860
812#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
813 "bank_intlv=cs0_cs1;" \
814 "en_cpc:cpc2;"
815#else
816#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
817#endif
818
York Sunb5b06fb2012-12-23 19:25:27 +0000819#define CONFIG_EXTRA_ENV_SETTINGS \
Shaveta Leekha38e0e152014-09-04 11:43:57 +0530820 HWCONFIG \
York Sunb5b06fb2012-12-23 19:25:27 +0000821 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
822 "netdev=eth0\0" \
823 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
824 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
825 "tftpflash=tftpboot $loadaddr $uboot && " \
826 "protect off $ubootaddr +$filesize && " \
827 "erase $ubootaddr +$filesize && " \
828 "cp.b $loadaddr $ubootaddr $filesize && " \
829 "protect on $ubootaddr +$filesize && " \
830 "cmp.b $loadaddr $ubootaddr $filesize\0" \
831 "consoledev=ttyS0\0" \
832 "ramdiskaddr=2000000\0" \
833 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
834 "fdtaddr=c00000\0" \
835 "fdtfile=b4860qds/b4860qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500836 "bdev=sda3\0"
York Sunb5b06fb2012-12-23 19:25:27 +0000837
838/* For emulation this causes u-boot to jump to the start of the proof point
839 app code automatically */
840#define CONFIG_PROOF_POINTS \
841 "setenv bootargs root=/dev/$bdev rw " \
842 "console=$consoledev,$baudrate $othbootargs;" \
843 "cpu 1 release 0x29000000 - - -;" \
844 "cpu 2 release 0x29000000 - - -;" \
845 "cpu 3 release 0x29000000 - - -;" \
846 "cpu 4 release 0x29000000 - - -;" \
847 "cpu 5 release 0x29000000 - - -;" \
848 "cpu 6 release 0x29000000 - - -;" \
849 "cpu 7 release 0x29000000 - - -;" \
850 "go 0x29000000"
851
852#define CONFIG_HVBOOT \
853 "setenv bootargs config-addr=0x60000000; " \
854 "bootm 0x01000000 - 0x00f00000"
855
856#define CONFIG_ALU \
857 "setenv bootargs root=/dev/$bdev rw " \
858 "console=$consoledev,$baudrate $othbootargs;" \
859 "cpu 1 release 0x01000000 - - -;" \
860 "cpu 2 release 0x01000000 - - -;" \
861 "cpu 3 release 0x01000000 - - -;" \
862 "cpu 4 release 0x01000000 - - -;" \
863 "cpu 5 release 0x01000000 - - -;" \
864 "cpu 6 release 0x01000000 - - -;" \
865 "cpu 7 release 0x01000000 - - -;" \
866 "go 0x01000000"
867
868#define CONFIG_LINUX \
869 "setenv bootargs root=/dev/ram rw " \
870 "console=$consoledev,$baudrate $othbootargs;" \
871 "setenv ramdiskaddr 0x02000000;" \
872 "setenv fdtaddr 0x00c00000;" \
873 "setenv loadaddr 0x1000000;" \
874 "bootm $loadaddr $ramdiskaddr $fdtaddr"
875
876#define CONFIG_HDBOOT \
877 "setenv bootargs root=/dev/$bdev rw " \
878 "console=$consoledev,$baudrate $othbootargs;" \
879 "tftp $loadaddr $bootfile;" \
880 "tftp $fdtaddr $fdtfile;" \
881 "bootm $loadaddr - $fdtaddr"
882
883#define CONFIG_NFSBOOTCOMMAND \
884 "setenv bootargs root=/dev/nfs rw " \
885 "nfsroot=$serverip:$rootpath " \
886 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
887 "console=$consoledev,$baudrate $othbootargs;" \
888 "tftp $loadaddr $bootfile;" \
889 "tftp $fdtaddr $fdtfile;" \
890 "bootm $loadaddr - $fdtaddr"
891
892#define CONFIG_RAMBOOTCOMMAND \
893 "setenv bootargs root=/dev/ram rw " \
894 "console=$consoledev,$baudrate $othbootargs;" \
895 "tftp $ramdiskaddr $ramdiskfile;" \
896 "tftp $loadaddr $bootfile;" \
897 "tftp $fdtaddr $fdtfile;" \
898 "bootm $loadaddr $ramdiskaddr $fdtaddr"
899
900#define CONFIG_BOOTCOMMAND CONFIG_LINUX
901
York Sunb5b06fb2012-12-23 19:25:27 +0000902#include <asm/fsl_secure_boot.h>
York Sunb5b06fb2012-12-23 19:25:27 +0000903
York Sunb5b06fb2012-12-23 19:25:27 +0000904#endif /* __CONFIG_H */