blob: 7945016624da55dd15f9a0d0ab2a3454ad3a9d3e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01002/*-
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
Remy Böhmerc0d722f2008-12-13 22:51:58 +01004 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01005 * All rights reserved.
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01006 */
7
8#ifndef USB_EHCI_H
9#define USB_EHCI_H
10
Marek Vasutb9596552013-07-10 03:16:31 +020011#include <usb.h>
Marek Vasutb43cdf92018-08-08 14:29:55 +020012#include <generic-phy.h>
Marek Vasutb9596552013-07-10 03:16:31 +020013
Bin Meng99c22552017-07-19 21:50:05 +080014/* Section 2.2.3 - N_PORTS */
15#define MAX_HC_PORTS 15
Remy Böhmerc0d722f2008-12-13 22:51:58 +010016
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010017/*
18 * Register Space.
19 */
20struct ehci_hccr {
michaeldb632992008-12-10 17:55:19 +010021 uint32_t cr_capbase;
22#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
23#define HC_VERSION(p) (((p) >> 16) & 0xffff)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010024 uint32_t cr_hcsparams;
Remy Böhmerc0d722f2008-12-13 22:51:58 +010025#define HCS_PPC(p) ((p) & (1 << 4))
26#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
michael51ab1422008-12-11 13:43:55 +010027#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010028 uint32_t cr_hccparams;
29 uint8_t cr_hcsp_portrt[8];
Jason Kridner69716c12011-04-20 08:54:16 -050030} __attribute__ ((packed, aligned(4)));
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010031
32struct ehci_hcor {
33 uint32_t or_usbcmd;
michael51ab1422008-12-11 13:43:55 +010034#define CMD_PARK (1 << 11) /* enable "park" */
35#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
michael51ab1422008-12-11 13:43:55 +010036#define CMD_LRESET (1 << 7) /* partial reset */
Masahiro Yamadac02bf452014-11-05 23:11:10 +090037#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
38#define CMD_ASE (1 << 5) /* async schedule enable */
michael51ab1422008-12-11 13:43:55 +010039#define CMD_PSE (1 << 4) /* periodic schedule enable */
40#define CMD_RESET (1 << 1) /* reset HC not bus */
41#define CMD_RUN (1 << 0) /* start/stop HC */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010042 uint32_t or_usbsts;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020043#define STS_ASS (1 << 15)
Patrick Georgi8f62ca62013-03-06 14:08:31 +000044#define STS_PSS (1 << 14)
michael51ab1422008-12-11 13:43:55 +010045#define STS_HALT (1 << 12)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010046 uint32_t or_usbintr;
Damien Dusha29c6fbe2010-10-14 15:27:06 +020047#define INTR_UE (1 << 0) /* USB interrupt enable */
48#define INTR_UEE (1 << 1) /* USB error interrupt enable */
49#define INTR_PCE (1 << 2) /* Port change detect enable */
50#define INTR_SEE (1 << 4) /* system error enable */
51#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010052 uint32_t or_frindex;
53 uint32_t or_ctrldssegment;
54 uint32_t or_periodiclistbase;
55 uint32_t or_asynclistaddr;
Simon Glass9ab4ce22012-02-27 10:52:47 +000056 uint32_t _reserved_0_;
57 uint32_t or_burstsize;
58 uint32_t or_txfilltuning;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020059#define TXFIFO_THRESH_MASK (0x3f << 16)
Simon Glass9ab4ce22012-02-27 10:52:47 +000060#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
61 uint32_t _reserved_1_[6];
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010062 uint32_t or_configflag;
michael51ab1422008-12-11 13:43:55 +010063#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
Bin Meng99c22552017-07-19 21:50:05 +080064 uint32_t or_portsc[MAX_HC_PORTS];
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020065#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
66#define PORTSC_PSPD_FS 0x0
67#define PORTSC_PSPD_LS 0x1
68#define PORTSC_PSPD_HS 0x2
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010069 uint32_t or_systune;
Jason Kridner69716c12011-04-20 08:54:16 -050070} __attribute__ ((packed, aligned(4)));
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010071
michael51ab1422008-12-11 13:43:55 +010072#define USBMODE 0x68 /* USB Device mode */
73#define USBMODE_SDIS (1 << 3) /* Stream disable */
74#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
75#define USBMODE_CM_HC (3 << 0) /* host controller mode */
76#define USBMODE_CM_IDLE (0 << 0) /* idle state */
77
michaeldb632992008-12-10 17:55:19 +010078/* Interface descriptor */
79struct usb_linux_interface_descriptor {
80 unsigned char bLength;
81 unsigned char bDescriptorType;
82 unsigned char bInterfaceNumber;
83 unsigned char bAlternateSetting;
84 unsigned char bNumEndpoints;
85 unsigned char bInterfaceClass;
86 unsigned char bInterfaceSubClass;
87 unsigned char bInterfaceProtocol;
88 unsigned char iInterface;
89} __attribute__ ((packed));
90
91/* Configuration descriptor information.. */
92struct usb_linux_config_descriptor {
93 unsigned char bLength;
94 unsigned char bDescriptorType;
95 unsigned short wTotalLength;
96 unsigned char bNumInterfaces;
97 unsigned char bConfigurationValue;
98 unsigned char iConfiguration;
99 unsigned char bmAttributes;
100 unsigned char MaxPower;
101} __attribute__ ((packed));
102
103#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
Alexey Brodkin9829ce22017-11-17 16:26:30 +0300104#define ehci_readl(x) be32_to_cpu(__raw_readl(x))
105#define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
michaeldb632992008-12-10 17:55:19 +0100106#else
Alexey Brodkin9829ce22017-11-17 16:26:30 +0300107#define ehci_readl(x) readl(x)
108#define ehci_writel(a, b) writel(b, a)
michaeldb632992008-12-10 17:55:19 +0100109#endif
110
111#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
112#define hc32_to_cpu(x) be32_to_cpu((x))
113#define cpu_to_hc32(x) cpu_to_be32((x))
114#else
115#define hc32_to_cpu(x) le32_to_cpu((x))
116#define cpu_to_hc32(x) cpu_to_le32((x))
117#endif
118
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100119#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
120#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
121#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
122#define EHCI_PS_PO (1 << 13) /* RW port owner */
123#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
124#define EHCI_PS_LS (3 << 10) /* RO line status */
125#define EHCI_PS_PR (1 << 8) /* RW port reset */
126#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
127#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
128#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
129#define EHCI_PS_OCA (1 << 4) /* RO over current active */
130#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
131#define EHCI_PS_PE (1 << 2) /* RW port enable */
132#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
133#define EHCI_PS_CS (1 << 0) /* RO connect status */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100134#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
135
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100136#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100137
138/*
139 * Schedule Interface Space.
140 *
141 * IMPORTANT: Software must ensure that no interface data structure
142 * reachable by the EHCI host controller spans a 4K page boundary!
143 *
144 * Periodic transfers (i.e. isochronous and interrupt transfers) are
145 * not supported.
146 */
147
148/* Queue Element Transfer Descriptor (qTD). */
149struct qTD {
Wolfgang Denk3ed16072010-10-19 16:13:15 +0200150 /* this part defined by EHCI spec */
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200151 uint32_t qt_next; /* see EHCI 3.5.1 */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100152#define QT_NEXT_TERMINATE 1
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200153 uint32_t qt_altnext; /* see EHCI 3.5.2 */
154 uint32_t qt_token; /* see EHCI 3.5.3 */
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200155#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
156#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
157#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
158#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
159#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
160#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
161#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
162#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
163#define QT_TOKEN_PID_OUT 0x0
164#define QT_TOKEN_PID_IN 0x1
165#define QT_TOKEN_PID_SETUP 0x2
166#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
167#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
168#define QT_TOKEN_STATUS_ACTIVE 0x80
169#define QT_TOKEN_STATUS_HALTED 0x40
170#define QT_TOKEN_STATUS_DATBUFERR 0x20
171#define QT_TOKEN_STATUS_BABBLEDET 0x10
172#define QT_TOKEN_STATUS_XACTERR 0x08
173#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
174#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
175#define QT_TOKEN_STATUS_PERR 0x01
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200176#define QT_BUFFER_CNT 5
177 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
178 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
Wolfgang Denk3ed16072010-10-19 16:13:15 +0200179 /* pad struct for 32 byte alignment */
180 uint32_t unused[3];
Wolfgang Denk8b675fe2010-10-20 21:08:17 +0200181};
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100182
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200183#define EHCI_PAGE_SIZE 4096
184
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100185/* Queue Head (QH). */
186struct QH {
187 uint32_t qh_link;
188#define QH_LINK_TERMINATE 1
189#define QH_LINK_TYPE_ITD 0
190#define QH_LINK_TYPE_QH 2
191#define QH_LINK_TYPE_SITD 4
192#define QH_LINK_TYPE_FSTN 6
193 uint32_t qh_endpt1;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200194#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
195#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
196#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
197#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
198#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
199#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
200#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
201#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
202#define QH_ENDPT1_EPS_FS 0x0
203#define QH_ENDPT1_EPS_LS 0x1
204#define QH_ENDPT1_EPS_HS 0x2
205#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
206#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
207#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100208 uint32_t qh_endpt2;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200209#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
210#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
211#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
212#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
213#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100214 uint32_t qh_curtd;
215 struct qTD qh_overlay;
Stefan Roesedaa2daf2009-01-21 17:12:19 +0100216 /*
217 * Add dummy fill value to make the size of this struct
218 * aligned to 32 bytes
219 */
Patrick Georgi8f62ca62013-03-06 14:08:31 +0000220 union {
Vincent Palatin61755c72013-03-06 14:08:32 +0000221 uint32_t fill[4];
Patrick Georgi8f62ca62013-03-06 14:08:31 +0000222 void *buffer;
223 };
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100224};
225
Simon Glass7372b5b2015-03-25 12:22:26 -0600226/* Tweak flags for EHCI, used to control operation */
227enum {
228 /* don't use or_configflag in init */
229 EHCI_TWEAK_NO_INIT_CF = 1 << 0,
230};
231
Simon Glassdeb85082015-03-25 12:22:27 -0600232struct ehci_ctrl;
233
234struct ehci_ops {
235 void (*set_usb_mode)(struct ehci_ctrl *ctrl);
236 int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
237 void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
238 uint32_t *reg);
239 uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
Mateusz Kulikowski3f9f8a52016-03-31 23:12:17 +0200240 int (*init_after_reset)(struct ehci_ctrl *ctrl);
Simon Glassdeb85082015-03-25 12:22:27 -0600241};
242
Marek Vasutb9596552013-07-10 03:16:31 +0200243struct ehci_ctrl {
Stephen Warren49b4c5c2015-08-20 17:38:05 -0600244 enum usb_init_type init;
Marek Vasutb9596552013-07-10 03:16:31 +0200245 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
246 struct ehci_hcor *hcor;
247 int rootdev;
248 uint16_t portreset;
249 struct QH qh_list __aligned(USB_DMA_MINALIGN);
250 struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
251 uint32_t *periodic_list;
Hans de Goede36b73102014-09-20 16:51:25 +0200252 int periodic_schedules;
Marek Vasutb9596552013-07-10 03:16:31 +0200253 int ntds;
Simon Glassdeb85082015-03-25 12:22:27 -0600254 struct ehci_ops ops;
Simon Glassc4a31412015-03-25 12:22:19 -0600255 void *priv; /* client's private data */
Marek Vasutb9596552013-07-10 03:16:31 +0200256};
257
Simon Glassc4a31412015-03-25 12:22:19 -0600258/**
Simon Glassdeb85082015-03-25 12:22:27 -0600259 * ehci_set_controller_info() - Set up private data for the controller
Simon Glassc4a31412015-03-25 12:22:19 -0600260 *
261 * This function can be called in ehci_hcd_init() to tell the EHCI layer
262 * about the controller's private data pointer. Then in the above functions
Simon Glassdeb85082015-03-25 12:22:27 -0600263 * this can be accessed given the struct ehci_ctrl pointer. Also special
264 * EHCI operation methods can be provided if required
Simon Glassc4a31412015-03-25 12:22:19 -0600265 *
266 * @index: Controller number to set
267 * @priv: Controller pointer
Simon Glassdeb85082015-03-25 12:22:27 -0600268 * @ops: Controller operations, or NULL to use default
Simon Glassc4a31412015-03-25 12:22:19 -0600269 */
Simon Glassdeb85082015-03-25 12:22:27 -0600270void ehci_set_controller_priv(int index, void *priv,
271 const struct ehci_ops *ops);
Simon Glassc4a31412015-03-25 12:22:19 -0600272
273/**
274 * ehci_get_controller_priv() - Get controller private data
275 *
276 * @index Controller number to get
277 * @return controller pointer for this index
278 */
279void *ehci_get_controller_priv(int index);
280
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100281/* Low level init functions */
Troy Kisky127efc42013-10-10 15:27:57 -0700282int ehci_hcd_init(int index, enum usb_init_type init,
283 struct ehci_hccr **hccr, struct ehci_hcor **hcor);
Lucas Stach676ae062012-09-26 00:14:35 +0200284int ehci_hcd_stop(int index);
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100285
Simon Glass46b01792015-03-25 12:22:29 -0600286int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
287 struct ehci_hcor *hcor, const struct ehci_ops *ops,
288 uint tweaks, enum usb_init_type init);
289int ehci_deregister(struct udevice *dev);
290extern struct dm_usb_ops ehci_usb_ops;
291
Marek Vasutb43cdf92018-08-08 14:29:55 +0200292/* EHCI PHY functions */
293int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index);
294int ehci_shutdown_phy(struct udevice *dev, struct phy *phy);
295
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100296#endif /* USB_EHCI_H */