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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b55c0f8a98a624f38a2f52ee39c80ff747839925 / . / doc / usage / cmd / mtrr.rst
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2
3mtrr command
4============
5
6Synopis
7-------
8
9 mtrr [list]
10 mtrr set <reg> <type> <start> <size>
11 mtrr disable <reg>
12 mtrr enable
13
14
15Description
16-----------
17
18The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on
19an x86 machine. These register control cache behaviour in selected memory
20ranges.
21
22Note that the number of registers can vary between CPUs.
23
24
25mtrr [list]
26~~~~~~~~~~~
27
28List the MTRRs. The table shows the following information:
29
30Reg
31 Register number (the first is register 0)
32
33Valid
34 Shows Y if the register is valid (has bit 11 set), N if not
35
36Write-type
37 Shows the behaviour when writing to the memory region. The types are
38 abbreviated to fit a reasonable line length. Valid types shown below.
39
40 ====== ============== ====================================================
41 Value Type Meaning
42 ====== ============== ====================================================
43 0 Uncacheable Skip cache and write directly to memory
44 1 Combine Multiple writes can be combined into one transaction
45 4 Through Update cache and also write to memory
46 5 Protect Writes are prohibited
47 6 Back Update cache but don't write to memory
48 ====== ============== ====================================================
49
50Base
51 Base memory address from which the register controls behaviour
52
53Mask
54 Mask value, which also indicates the size
55
56Size
57 Length of memory region within which the register controls behaviour
58
59
60mtrr set
61~~~~~~~~
62
63This sets the value of a particular MTRR. Parameters are:
64
65reg
66 Register number to set, with 0 being the first
67
68type
69 Access type to set. See Write-type above for valid types. This uses the name
70 rather than its numeric value.
71
72start
73 Base memory address from which the register should control behaviour
74
75size
76 Length of memory region within which the register controls behaviour
77
78
79mtrr disable
80~~~~~~~~~~~~
81
82This disables a particular register, by clearing its `valid` bit (11).
83
84
85mtrr enable
86~~~~~~~~~~~
87
88This enables a particular register, by setting its `valid` bit (11).
89
90
91Example
92-------
93
94This shows disabling and enabling an MTRR, as well as setting its type::
95
96 => mtrr
97 CPU 0:
98 Reg Valid Write-type Base || Mask || Size ||
99 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
100 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
101 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
102 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
103 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
104 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000
105 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
106 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
107 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
108 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
109 => mtrr d 5
110 => mtrr
111 CPU 0:
112 Reg Valid Write-type Base || Mask || Size ||
113 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
114 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
115 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
116 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
117 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
118 5 N Combine 00000000d0000000 0000000ff0000000 0000000010000000
119 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
120 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
121 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
122 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
123 => mtrr e 5
124 => mtrr
125 CPU 0:
126 Reg Valid Write-type Base || Mask || Size ||
127 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
128 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
129 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
130 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
131 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
132 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000
133 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
134 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
135 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
136 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
137 => mtrr set 5 Uncacheable d0000000 10000000
138 => mtrr
139 CPU 0:
140 Reg Valid Write-type Base || Mask || Size ||
141 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
142 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
143 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
144 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
145 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
146 5 Y Uncacheable 00000000d0000000 0000000ff0000000 0000000010000000
147 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
148 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
149 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
150 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
151 =>