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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * armboot - Startup Code for SA1100 CPU
3 *
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02007 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
wdenkfe8c2802002-11-03 00:38:21 +00008 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +000010 */
11
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020012#include <asm-offsets.h>
wdenkfe8c2802002-11-03 00:38:21 +000013#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +000014
wdenkfe8c2802002-11-03 00:38:21 +000015/*
16 *************************************************************************
17 *
wdenkfe8c2802002-11-03 00:38:21 +000018 * Startup Code (reset vector)
19 *
20 * do important init only if we don't start from memory!
21 * relocate armboot to ram
22 * setup stack
23 * jump to second stage
24 *
25 *************************************************************************
26 */
27
Albert ARIBAUD41623c92014-04-15 16:13:51 +020028 .globl reset
Heiko Schochere30ceca2010-09-17 13:10:48 +020029
30reset:
31 /*
32 * set the cpu to SVC32 mode
33 */
34 mrs r0,cpsr
35 bic r0,r0,#0x1f
36 orr r0,r0,#0xd3
37 msr cpsr,r0
38
39 /*
40 * we do sys-critical inits only at reboot,
41 * not when booting from ram!
42 */
43#ifndef CONFIG_SKIP_LOWLEVEL_INIT
44 bl cpu_init_crit
45#endif
46
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000047 bl _main
Heiko Schochere30ceca2010-09-17 13:10:48 +020048
49/*------------------------------------------------------------------------------*/
50
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000051 .globl c_runtime_cpu_setup
52c_runtime_cpu_setup:
53
54 mov pc, lr
55
wdenkfe8c2802002-11-03 00:38:21 +000056/*
57 *************************************************************************
58 *
59 * CPU_init_critical registers
60 *
61 * setup important registers
62 * setup memory timing
63 *
64 *************************************************************************
65 */
66
67
Mike Williams16263082011-07-22 04:01:30 +000068/* Interrupt-Controller base address */
wdenkfe8c2802002-11-03 00:38:21 +000069IC_BASE: .word 0x90050000
70#define ICMR 0x04
71
72
73/* Reset-Controller */
74RST_BASE: .word 0x90030000
75#define RSRR 0x00
76#define RCSR 0x04
77
78
79/* PWR */
80PWR_BASE: .word 0x90020000
81#define PSPR 0x08
82#define PPCR 0x14
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083cpuspeed: .word CONFIG_SYS_CPUSPEED
wdenkfe8c2802002-11-03 00:38:21 +000084
85
86cpu_init_crit:
87 /*
88 * mask all IRQs
89 */
90 ldr r0, IC_BASE
91 mov r1, #0x00
92 str r1, [r0, #ICMR]
93
94 /* set clock speed */
95 ldr r0, PWR_BASE
96 ldr r1, cpuspeed
97 str r1, [r0, #PPCR]
98
99 /*
100 * before relocating, we have to setup RAM timing
101 * because memory timing is board-dependend, you will
wdenk400558b2005-04-02 23:52:25 +0000102 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +0000103 */
104 mov ip, lr
wdenk400558b2005-04-02 23:52:25 +0000105 bl lowlevel_init
wdenkfe8c2802002-11-03 00:38:21 +0000106 mov lr, ip
107
108 /*
109 * disable MMU stuff and enable I-cache
110 */
111 mrc p15,0,r0,c1,c0
112 bic r0, r0, #0x00002000 @ clear bit 13 (X)
113 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
114 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
Yuichiro Gotoba10b852016-02-25 10:23:34 +0900115 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
wdenkfe8c2802002-11-03 00:38:21 +0000116 mcr p15,0,r0,c1,c0
117
118 /*
119 * flush v4 I/D caches
120 */
121 mov r0, #0
122 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
123 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
124
125 mov pc, lr