Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | CONFIG_PPC=y |
Tom Rini | 278b90c | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
Tom Rini | a09fea1 | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 3 | CONFIG_ENV_SIZE=0x4000 |
| 4 | CONFIG_ENV_SECT_SIZE=0x10000 |
Tom Rini | 7cfbba3 | 2021-08-28 21:34:49 -0400 | [diff] [blame] | 5 | CONFIG_SYS_MALLOC_LEN=0x80000 |
Tom Rini | 20ecfbe | 2021-03-02 09:36:23 -0500 | [diff] [blame] | 6 | CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" |
Tom Rini | 2bba780 | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 7 | CONFIG_SYS_CLK_FREQ=66666667 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 8 | CONFIG_MPC83xx=y |
Mario Six | 93de253 | 2019-01-21 09:17:56 +0100 | [diff] [blame] | 9 | CONFIG_HIGH_BATS=y |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 10 | CONFIG_TARGET_MPC837XERDB=y |
Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 11 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y |
| 12 | CONFIG_SYSTEM_PLL_FACTOR_5_1=y |
| 13 | CONFIG_CORE_PLL_RATIO_2_1=y |
| 14 | CONFIG_PCI_HOST_MODE_ENABLE=y |
| 15 | CONFIG_PCI_INT_ARBITER1_ENABLE=y |
| 16 | CONFIG_BOOT_MEMORY_SPACE_LOW=y |
| 17 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
| 18 | CONFIG_TSEC1_MODE_RGMII=y |
| 19 | CONFIG_TSEC2_MODE_RGMII=y |
| 20 | CONFIG_LDP_PIN_MUX_STATE_0=y |
Mario Six | 30915ab | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 21 | CONFIG_BAT0=y |
| 22 | CONFIG_BAT0_NAME="SDRAM_LOWER" |
| 23 | CONFIG_BAT0_BASE=0x00000000 |
| 24 | CONFIG_BAT0_LENGTH_256_MBYTES=y |
| 25 | CONFIG_BAT0_ACCESS_RW=y |
| 26 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y |
| 27 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y |
| 28 | CONFIG_BAT0_USER_MODE_VALID=y |
| 29 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 30 | CONFIG_BAT1=y |
| 31 | CONFIG_BAT1_NAME="SDRAM_UPPER" |
| 32 | CONFIG_BAT1_BASE=0x10000000 |
| 33 | CONFIG_BAT1_LENGTH_256_MBYTES=y |
| 34 | CONFIG_BAT1_ACCESS_RW=y |
| 35 | CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y |
| 36 | CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y |
| 37 | CONFIG_BAT1_USER_MODE_VALID=y |
| 38 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 39 | CONFIG_BAT2=y |
| 40 | CONFIG_BAT2_NAME="IMMR" |
| 41 | CONFIG_BAT2_BASE=0xE0000000 |
| 42 | CONFIG_BAT2_LENGTH_8_MBYTES=y |
| 43 | CONFIG_BAT2_ACCESS_RW=y |
| 44 | CONFIG_BAT2_ICACHE_INHIBITED=y |
| 45 | CONFIG_BAT2_ICACHE_GUARDED=y |
| 46 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 47 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 48 | CONFIG_BAT2_USER_MODE_VALID=y |
| 49 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 50 | CONFIG_BAT3=y |
| 51 | CONFIG_BAT3_NAME="L2_SWITCH" |
| 52 | CONFIG_BAT3_BASE=0xF0000000 |
| 53 | CONFIG_BAT3_ACCESS_RW=y |
| 54 | CONFIG_BAT3_ICACHE_INHIBITED=y |
| 55 | CONFIG_BAT3_ICACHE_GUARDED=y |
| 56 | CONFIG_BAT3_DCACHE_INHIBITED=y |
| 57 | CONFIG_BAT3_DCACHE_GUARDED=y |
| 58 | CONFIG_BAT3_USER_MODE_VALID=y |
| 59 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y |
| 60 | CONFIG_BAT4=y |
| 61 | CONFIG_BAT4_NAME="FLASH" |
| 62 | CONFIG_BAT4_BASE=0xFE000000 |
| 63 | CONFIG_BAT4_LENGTH_32_MBYTES=y |
| 64 | CONFIG_BAT4_ACCESS_RW=y |
| 65 | CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y |
| 66 | CONFIG_BAT4_DCACHE_INHIBITED=y |
| 67 | CONFIG_BAT4_DCACHE_GUARDED=y |
| 68 | CONFIG_BAT4_USER_MODE_VALID=y |
| 69 | CONFIG_BAT4_SUPERVISOR_MODE_VALID=y |
| 70 | CONFIG_BAT5=y |
| 71 | CONFIG_BAT5_NAME="STACH_IN_DCACHE" |
| 72 | CONFIG_BAT5_BASE=0xE6000000 |
| 73 | CONFIG_BAT5_ACCESS_RW=y |
| 74 | CONFIG_BAT5_USER_MODE_VALID=y |
| 75 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y |
| 76 | CONFIG_BAT6=y |
| 77 | CONFIG_BAT6_NAME="PCI_MEM" |
| 78 | CONFIG_BAT6_BASE=0x80000000 |
| 79 | CONFIG_BAT6_LENGTH_256_MBYTES=y |
| 80 | CONFIG_BAT6_ACCESS_RW=y |
| 81 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y |
| 82 | CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y |
| 83 | CONFIG_BAT6_USER_MODE_VALID=y |
| 84 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y |
| 85 | CONFIG_BAT7=y |
| 86 | CONFIG_BAT7_NAME="PCI_MMIO" |
| 87 | CONFIG_BAT7_BASE=0x90000000 |
| 88 | CONFIG_BAT7_LENGTH_256_MBYTES=y |
| 89 | CONFIG_BAT7_ACCESS_RW=y |
| 90 | CONFIG_BAT7_ICACHE_INHIBITED=y |
| 91 | CONFIG_BAT7_ICACHE_GUARDED=y |
| 92 | CONFIG_BAT7_DCACHE_INHIBITED=y |
| 93 | CONFIG_BAT7_DCACHE_GUARDED=y |
| 94 | CONFIG_BAT7_USER_MODE_VALID=y |
| 95 | CONFIG_BAT7_SUPERVISOR_MODE_VALID=y |
Mario Six | 9c5df7a | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 96 | CONFIG_LBLAW0=y |
| 97 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 98 | CONFIG_LBLAW0_NAME="FLASH" |
| 99 | CONFIG_LBLAW0_LENGTH_8_MBYTES=y |
| 100 | CONFIG_LBLAW1=y |
| 101 | CONFIG_LBLAW1_BASE=0xE0600000 |
| 102 | CONFIG_LBLAW1_NAME="NAND" |
| 103 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y |
| 104 | CONFIG_LBLAW2=y |
| 105 | CONFIG_LBLAW2_BASE=0xF0000000 |
| 106 | CONFIG_LBLAW2_NAME="VSC7385" |
| 107 | CONFIG_LBLAW2_LENGTH_128_KBYTES=y |
Tom Rini | 344a0e4 | 2019-05-26 14:45:25 -0400 | [diff] [blame] | 108 | CONFIG_ELBC_BR0_OR0=y |
| 109 | CONFIG_BR0_OR0_NAME="FLASH" |
| 110 | CONFIG_BR0_OR0_BASE=0xFE000000 |
| 111 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 112 | CONFIG_OR0_AM_8_MBYTES=y |
| 113 | CONFIG_OR0_SCY_9=y |
| 114 | CONFIG_OR0_XACS_EXTENDED=y |
| 115 | CONFIG_OR0_EHTR_1_CYCLE=y |
| 116 | CONFIG_OR0_EAD_EXTRA=y |
| 117 | CONFIG_ELBC_BR1_OR1=y |
| 118 | CONFIG_BR1_OR1_NAME="NAND" |
| 119 | CONFIG_BR1_OR1_BASE=0xE0600000 |
| 120 | CONFIG_BR1_ERRORCHECKING_BOTH=y |
| 121 | CONFIG_BR1_MACHINE_FCM=y |
| 122 | CONFIG_OR1_SCY_1=y |
| 123 | CONFIG_OR1_CSCT_8_CYCLE=y |
| 124 | CONFIG_OR1_CST_ONE_CLOCK=y |
| 125 | CONFIG_OR1_CHT_TWO_CLOCK=y |
| 126 | CONFIG_OR1_TRLX_RELAXED=y |
| 127 | CONFIG_OR1_EHTR_8_CYCLE=y |
| 128 | CONFIG_ELBC_BR2_OR2=y |
| 129 | CONFIG_BR2_OR2_NAME="VSC7385" |
| 130 | CONFIG_BR2_OR2_BASE=0xF0000000 |
| 131 | CONFIG_OR2_AM_128_KBYTES=y |
| 132 | CONFIG_OR2_SCY_15=y |
| 133 | CONFIG_OR2_CSNT_EARLIER=y |
| 134 | CONFIG_OR2_XACS_EXTENDED=y |
| 135 | CONFIG_OR2_SETA_EXTERNAL=y |
| 136 | CONFIG_OR2_TRLX_RELAXED=y |
| 137 | CONFIG_OR2_EHTR_8_CYCLE=y |
| 138 | CONFIG_OR2_EAD_EXTRA=y |
Mario Six | be5abb0 | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 139 | CONFIG_HID0_FINAL_EMCP=y |
| 140 | CONFIG_HID0_FINAL_ICE=y |
| 141 | CONFIG_HID2_HBE=y |
Mario Six | 73df96a | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 142 | CONFIG_ACR_PIPE_DEP_4=y |
| 143 | CONFIG_ACR_RPTCNT_4=y |
Mario Six | e35012e | 2019-01-21 09:18:13 +0100 | [diff] [blame] | 144 | CONFIG_SPCR_TSECEP_3=y |
Tom Rini | 344a0e4 | 2019-05-26 14:45:25 -0400 | [diff] [blame] | 145 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 146 | CONFIG_LCRR_CLKDIV_8=y |
Simon Glass | 73223f0 | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
Mario Six | ff3bb0c | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 149 | CONFIG_SYS_EXTRA_OPTIONS="PCIE" |
Heiko Schocher | bb597c0 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 150 | CONFIG_BOOTDELAY=6 |
Sinan Akman | c8be85f | 2021-05-11 14:18:02 -0400 | [diff] [blame] | 151 | CONFIG_BOARD_LATE_INIT=y |
Adam Ford | 8ccf98b | 2018-07-29 13:13:29 -0500 | [diff] [blame] | 152 | CONFIG_MISC_INIT_R=y |
Sinan Akman | c8be85f | 2021-05-11 14:18:02 -0400 | [diff] [blame] | 153 | CONFIG_PCI_INIT_R=y |
Tom Rini | adad96e | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 154 | CONFIG_HUSH_PARSER=y |
Tuomas Tynkkynen | ad12dc1 | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 155 | CONFIG_CMD_IMLS=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 156 | CONFIG_CMD_I2C=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 157 | CONFIG_CMD_MMC=y |
Simon Glass | 6500ec7 | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 158 | CONFIG_CMD_PCI=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 159 | CONFIG_CMD_SATA=y |
| 160 | CONFIG_CMD_USB=y |
Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 161 | # CONFIG_CMD_SETEXPR is not set |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 162 | CONFIG_CMD_MII=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 163 | CONFIG_CMD_PING=y |
Chris Packham | c9032ce | 2017-04-29 15:20:28 +1200 | [diff] [blame] | 164 | CONFIG_CMD_DATE=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 165 | CONFIG_CMD_EXT2=y |
| 166 | CONFIG_CMD_FAT=y |
Sinan Akman | a2c48cb | 2020-04-04 01:16:47 -0400 | [diff] [blame] | 167 | CONFIG_OF_CONTROL=y |
Tom Rini | 20ecfbe | 2021-03-02 09:36:23 -0500 | [diff] [blame] | 168 | CONFIG_ENV_OVERWRITE=y |
Tom Rini | a09fea1 | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 169 | CONFIG_ENV_ADDR=0xFE080000 |
Sinan Akman | a2c48cb | 2020-04-04 01:16:47 -0400 | [diff] [blame] | 170 | CONFIG_DM=y |
Tuomas Tynkkynen | 9920d15 | 2017-12-08 15:36:17 +0200 | [diff] [blame] | 171 | CONFIG_FSL_SATA=y |
Tom Rini | 55dabcc | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 172 | CONFIG_SYS_I2C_LEGACY=y |
Tom Rini | 6d5d0c9 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 173 | CONFIG_SYS_I2C_FSL=y |
| 174 | CONFIG_SYS_FSL_I2C_OFFSET=0x3000 |
| 175 | CONFIG_SYS_I2C_SLAVE=0x7F |
| 176 | CONFIG_SYS_I2C_SPEED=400000 |
Mario Six | 07dea2e | 2018-03-28 14:38:19 +0200 | [diff] [blame] | 177 | CONFIG_FSL_ESDHC=y |
Masahiro Yamada | e856bdc | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 178 | CONFIG_MTD_NOR_FLASH=y |
Adam Ford | 2fe88d4 | 2018-10-14 15:10:50 -0500 | [diff] [blame] | 179 | CONFIG_FLASH_CFI_DRIVER=y |
| 180 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 181 | CONFIG_SYS_FLASH_PROTECTION=y |
| 182 | CONFIG_SYS_FLASH_CFI=y |
Sinan Akman | c8be85f | 2021-05-11 14:18:02 -0400 | [diff] [blame] | 183 | CONFIG_DM_ETH=y |
| 184 | CONFIG_DM_MDIO=y |
| 185 | CONFIG_DM_ETH_PHY=y |
| 186 | CONFIG_RGMII=y |
| 187 | CONFIG_MII=y |
Mario Six | 1715105 | 2018-03-28 14:38:18 +0200 | [diff] [blame] | 188 | CONFIG_TSEC_ENET=y |
Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 189 | CONFIG_SYS_NS16550=y |
Tom Rini | 645176d | 2016-09-08 16:31:26 -0400 | [diff] [blame] | 190 | CONFIG_USB=y |
Tom Rini | 64d6ac5 | 2017-05-12 22:33:28 -0400 | [diff] [blame] | 191 | CONFIG_USB_EHCI_HCD=y |