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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b798b8bac6f298a053bcfbeaf5e0b7eaddb7ca5f / . / post / lib_powerpc / threei.c
blob: 28c17df71e49b695afb229cee43455e1f0971ad4 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]2/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]5 */
6
7#include <common.h>
8
9/*
10 * CPU test
11 * Ternary instructions instr rA,rS,UIMM
12 *
13 * Logic instructions: ori, oris, xori, xoris
14 *
15 * The test contains a pre-built table of instructions, operands and
16 * expected results. For each table entry, the test will cyclically use
17 * different sets of operand registers and result registers.
18 */
19
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]20#include <post.h>
21#include "cpu_asm.h"
22
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]23#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]24
25extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
26extern ulong cpu_post_makecr (long v);
27
28static struct cpu_post_threei_s
29{
30 ulong cmd;
31 ulong op1;
32 ushort op2;
33 ulong res;
34} cpu_post_threei_table[] =
35{
36 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]37 OP_ORI,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]38 0x80000000,
39 0xffff,
40 0x8000ffff
41 },
42 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]43 OP_ORIS,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]44 0x00008000,
45 0xffff,
46 0xffff8000
47 },
48 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]49 OP_XORI,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]50 0x8000ffff,
51 0xffff,
52 0x80000000
53 },
54 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]55 OP_XORIS,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]56 0x00008000,
57 0xffff,
58 0xffff8000
59 },
60};
Mike Frysingerd2397812011-05-10 07:28:35 +0000[diff] [blame]61static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]62
63int cpu_post_test_threei (void)
64{
65 int ret = 0;
66 unsigned int i, reg;
67 int flag = disable_interrupts();
68
69 for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
70 {
71 struct cpu_post_threei_s *test = cpu_post_threei_table + i;
72
73 for (reg = 0; reg < 32 && ret == 0; reg++)
74 {
75 unsigned int reg0 = (reg + 0) % 32;
76 unsigned int reg1 = (reg + 1) % 32;
77 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]78 unsigned long code[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]79 {
80 ASM_STW(stk, 1, -4),
81 ASM_ADDI(stk, 1, -16),
82 ASM_STW(3, stk, 8),
83 ASM_STW(reg0, stk, 4),
84 ASM_STW(reg1, stk, 0),
85 ASM_LWZ(reg0, stk, 8),
86 ASM_11IX(test->cmd, reg1, reg0, test->op2),
87 ASM_STW(reg1, stk, 8),
88 ASM_LWZ(reg1, stk, 0),
89 ASM_LWZ(reg0, stk, 4),
90 ASM_LWZ(3, stk, 8),
91 ASM_ADDI(1, stk, 16),
92 ASM_LWZ(stk, 1, -4),
93 ASM_BLR,
94 };
95 ulong res;
96 ulong cr;
97
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]98 cr = 0;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]99 cpu_post_exec_21 (code, & cr, & res, test->op1);
100
101 ret = res == test->res && cr == 0 ? 0 : -1;
102
103 if (ret != 0)
104 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200[diff] [blame]105 post_log ("Error at threei test %d !\n", i);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]106 }
107 }
108 }
109
110 if (flag)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]111 enable_interrupts();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100[diff] [blame]112
113 return ret;
114}
115
116#endif