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Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Kumar Gala6525d512010-07-08 22:37:44 -05002 * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050028#include <asm/mmu.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050029#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050030#include <asm/fsl_pci.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050031#include <asm/fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060032#include <asm/fsl_serdes.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060033#include <spd_sdram.h>
Andy Fleming09f3e092006-09-13 10:34:18 -050034#include <miiphy.h>
Kumar Galab90d2542007-11-29 00:11:44 -060035#include <libfdt.h>
36#include <fdt_support.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050037
38#include "../common/cadmus.h"
39#include "../common/eeprom.h"
Matthew McClintockbf1dfff2006-06-28 10:46:13 -050040#include "../common/via.h"
Jon Loeligerd9b94f22005-07-25 14:05:07 -050041
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050042DECLARE_GLOBAL_DATA_PTR;
43
Jon Loeligerd9b94f22005-07-25 14:05:07 -050044void local_bus_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050045
Jon Loeligerd9b94f22005-07-25 14:05:07 -050046int checkboard (void)
47{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050050
51 /* PCI slot in USER bits CSR[6:7] by convention. */
52 uint pci_slot = get_pci_slot ();
53
Jon Loeligerd9b94f22005-07-25 14:05:07 -050054 uint cpu_board_rev = get_cpu_board_revision ();
55
56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
57 get_board_version (), pci_slot);
58
59 printf ("CPU Board Revision %d.%d (0x%04x)\n",
60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050062 /*
63 * Initialize local bus.
64 */
65 local_bus_init ();
66
Jon Loeligerd9b94f22005-07-25 14:05:07 -050067 /*
68 * Hack TSEC 3 and 4 IO voltages.
69 */
70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
71
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050072 ecm->eedr = 0xffffffff; /* clear ecm errors */
73 ecm->eeer = 0xffffffff; /* enable ecm errors */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050074 return 0;
75}
76
Jon Loeligerd9b94f22005-07-25 14:05:07 -050077/*
78 * Initialize Local Bus
79 */
80void
81local_bus_init(void)
82{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -050084 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050085
86 uint clkdiv;
87 uint lbc_hz;
88 sys_info_t sysinfo;
89
90 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -080091 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050092 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
93
94 gur->lbiuiplldcr1 = 0x00078080;
95 if (clkdiv == 16) {
96 gur->lbiuiplldcr0 = 0x7c0f1bf0;
97 } else if (clkdiv == 8) {
98 gur->lbiuiplldcr0 = 0x6c0f1bf0;
99 } else if (clkdiv == 4) {
100 gur->lbiuiplldcr0 = 0x5c0f1bf0;
101 }
102
103 lbc->lcrr |= 0x00030000;
104
105 asm("sync;isync;msync");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500106
107 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
108 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500109}
110
111/*
112 * Initialize SDRAM memory on the Local Bus.
113 */
Becky Bruce70961ba2010-12-17 17:17:57 -0600114void lbc_sdram_init(void)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500115{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500117
118 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500119 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500121 uint cpu_board_rev;
122 uint lsdmr_common;
123
Becky Bruce7ea38712010-12-17 17:17:59 -0600124 puts("LBC SDRAM: ");
125 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
126 "\n ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500127
128 /*
129 * Setup SDRAM Base and Option Registers
130 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500131 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
132 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500134 asm("msync");
135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
137 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500138 asm("msync");
139
140 /*
141 * MPC8548 uses "new" 15-16 style addressing.
142 */
143 cpu_board_rev = get_cpu_board_revision();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500145 lsdmr_common |= LSDMR_BSMA1516;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500146
147 /*
148 * Issue PRECHARGE ALL command.
149 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500150 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500151 asm("sync;msync");
152 *sdram_addr = 0xff;
153 ppcDcbf((unsigned long) sdram_addr);
154 udelay(100);
155
156 /*
157 * Issue 8 AUTO REFRESH commands.
158 */
159 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500160 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500161 asm("sync;msync");
162 *sdram_addr = 0xff;
163 ppcDcbf((unsigned long) sdram_addr);
164 udelay(100);
165 }
166
167 /*
168 * Issue 8 MODE-set command.
169 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500170 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500171 asm("sync;msync");
172 *sdram_addr = 0xff;
173 ppcDcbf((unsigned long) sdram_addr);
174 udelay(100);
175
176 /*
177 * Issue NORMAL OP command.
178 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500179 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500180 asm("sync;msync");
181 *sdram_addr = 0xff;
182 ppcDcbf((unsigned long) sdram_addr);
183 udelay(200); /* Overkill. Must wait > 200 bus cycles */
184
185#endif /* enable SDRAM init */
186}
187
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500188#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500189/* For some reason the Tundra PCI bridge shows up on itself as a
190 * different device. Work around that by refusing to configure it.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500191 */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500192void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500193
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500194static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500195 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700196 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
197 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600198 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700199 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
200 mpc85xx_config_via_usb, {0,0,0}},
201 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
202 mpc85xx_config_via_usb2, {0,0,0}},
203 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600204 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700205 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
206 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600207 {},
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500208};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500209
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500210static struct pci_controller pci1_hose = {
211 config_table: pci_mpc85xxcds_config_table};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500212#endif /* CONFIG_PCI */
213
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500214#ifdef CONFIG_PCI2
215static struct pci_controller pci2_hose;
216#endif /* CONFIG_PCI2 */
217
Kumar Gala7b626882009-11-04 11:15:29 -0600218void pci_init_board(void)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500219{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600221 struct fsl_pci_info pci_info;
Kumar Gala7b626882009-11-04 11:15:29 -0600222 u32 devdisr, pordevsr, io_sel;
223 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
224 int first_free_busno = 0;
Kumar Gala7b626882009-11-04 11:15:29 -0600225
226 devdisr = in_be32(&gur->devdisr);
227 pordevsr = in_be32(&gur->pordevsr);
228 porpllsr = in_be32(&gur->porpllsr);
229 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
230
231 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500232
233#ifdef CONFIG_PCI1
Kumar Gala7b626882009-11-04 11:15:29 -0600234 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
235 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
236 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
237 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500238
Kumar Gala7b626882009-11-04 11:15:29 -0600239 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600240 SET_STD_PCI_INFO(pci_info, 1);
241 set_next_law(pci_info.mem_phys,
242 law_size_bits(pci_info.mem_size), pci_info.law);
243 set_next_law(pci_info.io_phys,
244 law_size_bits(pci_info.io_size), pci_info.law);
245
246 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500247 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500248 (pci_32) ? 32 : 64,
249 (pci_speed == 33333000) ? "33" :
250 (pci_speed == 66666000) ? "66" : "unknown",
251 pci_clk_sel ? "sync" : "async",
252 pci_agent ? "agent" : "host",
Kumar Gala7b626882009-11-04 11:15:29 -0600253 pci_arb ? "arbiter" : "external-arbiter",
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600254 pci_info.regs);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500255
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600256 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala7b626882009-11-04 11:15:29 -0600257 &pci1_hose, first_free_busno);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500258
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500259#ifdef CONFIG_PCIX_CHECK
Kumar Gala7b626882009-11-04 11:15:29 -0600260 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500261 /* PCI-X init */
262 if (CONFIG_SYS_CLK_FREQ < 66000000)
263 printf("PCI-X will only work at 66 MHz\n");
264
265 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
266 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
267 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
268 }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500269#endif
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500270 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500271 printf("PCI: disabled\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500272 }
Kumar Gala7b626882009-11-04 11:15:29 -0600273
274 puts("\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500275#else
Kumar Gala7b626882009-11-04 11:15:29 -0600276 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500277#endif
278
279#ifdef CONFIG_PCI2
280{
Kumar Gala7b626882009-11-04 11:15:29 -0600281 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500282 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
283 if (pci_dual) {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500284 printf("PCI2: 32 bit, 66 MHz, %s\n",
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500285 pci2_clk_sel ? "sync" : "async");
286 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500287 printf("PCI2: disabled\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500288 }
289}
290#else
Kumar Gala7b626882009-11-04 11:15:29 -0600291 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500292#endif /* CONFIG_PCI2 */
293
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600294 fsl_pcie_init_board(first_free_busno);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500295}
Andy Fleming09f3e092006-09-13 10:34:18 -0500296
297int last_stage_init(void)
298{
Jon Loeligerf5012822006-10-20 15:54:34 -0500299 unsigned short temp;
Andy Fleming09f3e092006-09-13 10:34:18 -0500300
301 /* Change the resistors for the PHY */
302 /* This is needed to get the RGMII working for the 1.3+
303 * CDS cards */
304 if (get_board_version() == 0x13) {
Kim Phillips255a35772007-05-16 16:52:19 -0500305 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500306 TSEC1_PHY_ADDR, 29, 18);
307
Kim Phillips255a35772007-05-16 16:52:19 -0500308 miiphy_read(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500309 TSEC1_PHY_ADDR, 30, &temp);
310
311 temp = (temp & 0xf03f);
312 temp |= 2 << 9; /* 36 ohm */
313 temp |= 2 << 6; /* 39 ohm */
314
Kim Phillips255a35772007-05-16 16:52:19 -0500315 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500316 TSEC1_PHY_ADDR, 30, temp);
317
Kim Phillips255a35772007-05-16 16:52:19 -0500318 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500319 TSEC1_PHY_ADDR, 29, 3);
320
Kim Phillips255a35772007-05-16 16:52:19 -0500321 miiphy_write(CONFIG_TSEC1_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500322 TSEC1_PHY_ADDR, 30, 0x8000);
323 }
324
325 return 0;
326}
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500327
328
Kumar Galab90d2542007-11-29 00:11:44 -0600329#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500330void ft_pci_setup(void *blob, bd_t *bd)
331{
Kumar Gala6525d512010-07-08 22:37:44 -0500332 FT_FSL_PCI_SETUP;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500333}
334#endif