blob: 6eca9f23dc74180e39e533e429696085bc569945 [file] [log] [blame]
Scott McNutt9cc83372006-06-08 13:37:39 -04001/*
2 * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*------------------------------------------------------------------------
28 * BOARD/CPU
29 *----------------------------------------------------------------------*/
30#define CONFIG_EP1S10 1 /* EP1S10 board */
31#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
32
33#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
34#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
35#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
36
37/*------------------------------------------------------------------------
38 * CACHE -- the following will support II/s and II/f. The II/s does not
39 * have dcache, so the cache instructions will behave as NOPs.
40 *----------------------------------------------------------------------*/
41#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
42#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
43#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
44#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
45
46/*------------------------------------------------------------------------
47 * MEMORY BASE ADDRESSES
48 *----------------------------------------------------------------------*/
49#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
50#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
51#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
52#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
53#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
54#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */
55
56/*------------------------------------------------------------------------
57 * MEMORY ORGANIZATION
58 * -Monitor at top.
59 * -The heap is placed below the monitor.
60 * -Global data is placed below the heap.
61 * -The stack is placed below global data (&grows down).
62 *----------------------------------------------------------------------*/
63#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
64#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
65#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */
66
67#define CFG_MONITOR_BASE TEXT_BASE
68#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
69#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
70#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
71
72/*------------------------------------------------------------------------
73 * FLASH (AM29LV065D)
74 *----------------------------------------------------------------------*/
75#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
76#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
77#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
78#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
79
80/*------------------------------------------------------------------------
81 * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
82 * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
83 * of flash memory. This will keep the environment in user region
84 * of flash. NOTE: the monitor length must be multiple of sector size
85 * (which is common practice).
86 *----------------------------------------------------------------------*/
87#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
88#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
89#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
90#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
91
92/*------------------------------------------------------------------------
93 * CONSOLE
94 *----------------------------------------------------------------------*/
95#if defined(CONFIG_CONSOLE_JTAG)
96#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
97#else
98#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
99#endif
100
101#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
102#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
103#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
104
105#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
106
107/*------------------------------------------------------------------------
108 * EPCS Device -- None for stratix.
109 *----------------------------------------------------------------------*/
110#undef CFG_NIOS_EPCSBASE
111
112/*------------------------------------------------------------------------
113 * DEBUG
114 *----------------------------------------------------------------------*/
115#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
116
117/*------------------------------------------------------------------------
118 * TIMEBASE --
119 *
120 * The high res timer defaults to 1 msec. Since it includes the period
121 * registers, we can slow it down to 10 msec using TMRCNT. If the default
122 * period is acceptable, TMRCNT can be left undefined.
123 *----------------------------------------------------------------------*/
124#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
125#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
126#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
127#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
128#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
129
130/*------------------------------------------------------------------------
131 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
132 * must implement its own led routines -- since leds are board-specific.
133 *----------------------------------------------------------------------*/
134#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
135#define CONFIG_STATUS_LED /* Enable status driver */
136
137#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
138#define STATUS_LED_STATE 1 /* Blinking */
139#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */
140
141/*------------------------------------------------------------------------
142 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
143 * and really doesn't need any additional clutter. So I choose the lazy
144 * way out to avoid changes there -- define the base address to ensure
145 * cache bypass so there's no need to monkey with inx/outx macros.
146 *----------------------------------------------------------------------*/
147#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
148#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
149#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
150#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
151
152#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
153#define CONFIG_NETMASK 255.255.255.0
154#define CONFIG_IPADDR 192.168.2.21
155#define CONFIG_SERVERIP 192.168.2.16
156
157/*------------------------------------------------------------------------
158 * COMMANDS
159 *----------------------------------------------------------------------*/
160#define CONFIG_COMMANDS (CFG_CMD_BDI | \
161 CFG_CMD_DHCP | \
162 CFG_CMD_ECHO | \
163 CFG_CMD_ENV | \
164 CFG_CMD_FLASH | \
165 CFG_CMD_IMI | \
166 CFG_CMD_IRQ | \
167 CFG_CMD_LOADS | \
168 CFG_CMD_LOADB | \
169 CFG_CMD_MEMORY | \
170 CFG_CMD_MISC | \
171 CFG_CMD_NET | \
172 CFG_CMD_PING | \
173 CFG_CMD_RUN | \
174 CFG_CMD_SAVES )
175#include <cmd_confdefs.h>
176
177/*------------------------------------------------------------------------
178 * MISC
179 *----------------------------------------------------------------------*/
180#define CFG_LONGHELP /* Provide extended help*/
181#define CFG_PROMPT "==> " /* Command prompt */
182#define CFG_CBSIZE 256 /* Console I/O buf size */
183#define CFG_MAXARGS 16 /* Max command args */
184#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
185#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
186#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
187#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
188#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
189
190#define CFG_HUSH_PARSER
191#define CFG_PROMPT_HUSH_PS2 "> "
192
193#endif /* __CONFIG_H */