| Patrick Delaunay | 3d2d115 | 2018-03-12 10:46:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright : STMicroelectronics 2018 |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <dt-bindings/clock/stm32mp1-clksrc.h> |
| 8 | #include "stm32mp157-u-boot.dtsi" |
| 9 | #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" |
| 10 | |
| 11 | / { |
| 12 | aliases { |
| 13 | mmc0 = &sdmmc1; |
| Patrick Delaunay | 0ed232b | 2018-03-20 10:54:52 +0100 | [diff] [blame] | 14 | mmc1 = &sdmmc2; |
| Patrick Delaunay | 3d2d115 | 2018-03-12 10:46:17 +0100 | [diff] [blame] | 15 | i2c3 = &i2c4; |
| 16 | }; |
| 17 | }; |
| 18 | |
| 19 | &uart4_pins_a { |
| 20 | u-boot,dm-pre-reloc; |
| 21 | pins1 { |
| 22 | u-boot,dm-pre-reloc; |
| 23 | }; |
| 24 | pins2 { |
| 25 | u-boot,dm-pre-reloc; |
| 26 | }; |
| 27 | }; |
| 28 | |
| 29 | &i2c4_pins_a { |
| 30 | u-boot,dm-pre-reloc; |
| 31 | pins { |
| 32 | u-boot,dm-pre-reloc; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | &uart4 { |
| 37 | u-boot,dm-pre-reloc; |
| 38 | }; |
| 39 | |
| 40 | &i2c4 { |
| 41 | u-boot,dm-pre-reloc; |
| 42 | }; |
| 43 | |
| 44 | &pmic { |
| 45 | u-boot,dm-pre-reloc; |
| 46 | }; |
| 47 | |
| 48 | /* CLOCK init */ |
| 49 | &rcc_clk { |
| 50 | st,clksrc = < |
| 51 | CLK_MPU_PLL1P |
| 52 | CLK_AXI_PLL2P |
| 53 | CLK_MCU_PLL3P |
| 54 | CLK_PLL12_HSE |
| 55 | CLK_PLL3_HSE |
| 56 | CLK_PLL4_HSE |
| 57 | CLK_RTC_LSE |
| 58 | CLK_MCO1_DISABLED |
| 59 | CLK_MCO2_DISABLED |
| 60 | >; |
| 61 | |
| 62 | st,clkdiv = < |
| 63 | 1 /*MPU*/ |
| 64 | 0 /*AXI*/ |
| 65 | 0 /*MCU*/ |
| 66 | 1 /*APB1*/ |
| 67 | 1 /*APB2*/ |
| 68 | 1 /*APB3*/ |
| 69 | 1 /*APB4*/ |
| 70 | 2 /*APB5*/ |
| 71 | 23 /*RTC*/ |
| 72 | 0 /*MCO1*/ |
| 73 | 0 /*MCO2*/ |
| 74 | >; |
| 75 | |
| 76 | st,pkcs = < |
| 77 | CLK_CKPER_DISABLED |
| 78 | CLK_SDMMC12_PLL3R |
| 79 | CLK_I2C46_PCLK5 |
| 80 | CLK_I2C12_PCLK1 |
| Patrick Delaunay | 0ed232b | 2018-03-20 10:54:52 +0100 | [diff] [blame] | 81 | CLK_SDMMC3_PLL3R |
| Patrick Delaunay | 3d2d115 | 2018-03-12 10:46:17 +0100 | [diff] [blame] | 82 | CLK_I2C35_PCLK1 |
| 83 | CLK_UART1_PCLK5 |
| 84 | CLK_UART24_PCLK1 |
| 85 | CLK_UART35_PCLK1 |
| 86 | CLK_UART6_PCLK2 |
| 87 | CLK_UART78_PCLK1 |
| 88 | >; |
| 89 | |
| 90 | /* VCO = 1300.0 MHz => P = 650 (CPU) */ |
| 91 | pll1: st,pll@0 { |
| 92 | cfg = < 2 80 0 0 0 PQR(1,0,0) >; |
| 93 | frac = < 0x800 >; |
| 94 | u-boot,dm-pre-reloc; |
| 95 | }; |
| 96 | |
| 97 | /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ |
| 98 | pll2: st,pll@1 { |
| 99 | cfg = < 2 65 1 0 0 PQR(1,1,1) >; |
| 100 | frac = < 0x1400 >; |
| 101 | u-boot,dm-pre-reloc; |
| 102 | }; |
| 103 | |
| 104 | /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */ |
| 105 | pll3: st,pll@2 { |
| 106 | cfg = < 3 128 3 20 7 PQR(1,1,1) >; |
| 107 | u-boot,dm-pre-reloc; |
| 108 | }; |
| 109 | |
| 110 | /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ |
| 111 | pll4: st,pll@3 { |
| 112 | cfg = < 5 126 8 8 8 PQR(1,1,1) >; |
| 113 | u-boot,dm-pre-reloc; |
| 114 | }; |
| 115 | }; |
| 116 | |
| 117 | /* SPL part **************************************/ |
| 118 | /* MMC1 boot */ |
| 119 | &sdmmc1_b4_pins_a { |
| 120 | u-boot,dm-spl; |
| 121 | pins { |
| 122 | u-boot,dm-spl; |
| 123 | }; |
| 124 | }; |
| 125 | |
| 126 | &sdmmc1_dir_pins_a { |
| 127 | u-boot,dm-spl; |
| 128 | pins { |
| 129 | u-boot,dm-spl; |
| 130 | }; |
| 131 | }; |
| 132 | |
| 133 | &sdmmc1 { |
| 134 | u-boot,dm-spl; |
| 135 | }; |
| Patrick Delaunay | 0ed232b | 2018-03-20 10:54:52 +0100 | [diff] [blame] | 136 | |
| 137 | /* MMC2 boot */ |
| 138 | &sdmmc2_b4_pins_a { |
| 139 | u-boot,dm-spl; |
| 140 | pins { |
| 141 | u-boot,dm-spl; |
| 142 | }; |
| 143 | }; |
| 144 | |
| 145 | &sdmmc2_d47_pins_a { |
| 146 | u-boot,dm-spl; |
| 147 | pins { |
| 148 | u-boot,dm-spl; |
| 149 | }; |
| 150 | }; |
| 151 | |
| 152 | &sdmmc2 { |
| 153 | u-boot,dm-spl; |
| 154 | }; |