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Tom Rini5270df22018-04-07 09:15:06 -04001/*
2 * Register definitions for the Atmel AT32/AT91 SPI Controller
3 */
4
5/* Register offsets */
6#define ATMEL_SPI_CR 0x0000
7#define ATMEL_SPI_MR 0x0004
8#define ATMEL_SPI_RDR 0x0008
9#define ATMEL_SPI_TDR 0x000c
10#define ATMEL_SPI_SR 0x0010
11#define ATMEL_SPI_IER 0x0014
12#define ATMEL_SPI_IDR 0x0018
13#define ATMEL_SPI_IMR 0x001c
14#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x))
15#define ATMEL_SPI_VERSION 0x00fc
16
17/* Bits in CR */
18#define ATMEL_SPI_CR_SPIEN BIT(0)
19#define ATMEL_SPI_CR_SPIDIS BIT(1)
20#define ATMEL_SPI_CR_SWRST BIT(7)
21#define ATMEL_SPI_CR_LASTXFER BIT(24)
22
23/* Bits in MR */
24#define ATMEL_SPI_MR_MSTR BIT(0)
25#define ATMEL_SPI_MR_PS BIT(1)
26#define ATMEL_SPI_MR_PCSDEC BIT(2)
27#define ATMEL_SPI_MR_FDIV BIT(3)
28#define ATMEL_SPI_MR_MODFDIS BIT(4)
29#define ATMEL_SPI_MR_WDRBT BIT(5)
30#define ATMEL_SPI_MR_LLB BIT(7)
31#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
32#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
33
34/* Bits in RDR */
35#define ATMEL_SPI_RDR_RD(x) (x)
36#define ATMEL_SPI_RDR_PCS(x) ((x) << 16)
37
38/* Bits in TDR */
39#define ATMEL_SPI_TDR_TD(x) (x)
40#define ATMEL_SPI_TDR_PCS(x) ((x) << 16)
41#define ATMEL_SPI_TDR_LASTXFER BIT(24)
42
43/* Bits in SR/IER/IDR/IMR */
44#define ATMEL_SPI_SR_RDRF BIT(0)
45#define ATMEL_SPI_SR_TDRE BIT(1)
46#define ATMEL_SPI_SR_MODF BIT(2)
47#define ATMEL_SPI_SR_OVRES BIT(3)
48#define ATMEL_SPI_SR_ENDRX BIT(4)
49#define ATMEL_SPI_SR_ENDTX BIT(5)
50#define ATMEL_SPI_SR_RXBUFF BIT(6)
51#define ATMEL_SPI_SR_TXBUFE BIT(7)
52#define ATMEL_SPI_SR_NSSR BIT(8)
53#define ATMEL_SPI_SR_TXEMPTY BIT(9)
54#define ATMEL_SPI_SR_SPIENS BIT(16)
55
56/* Bits in CSRx */
57#define ATMEL_SPI_CSRx_CPOL BIT(0)
58#define ATMEL_SPI_CSRx_NCPHA BIT(1)
59#define ATMEL_SPI_CSRx_CSAAT BIT(3)
60#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
61#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
62#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0)
63#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16)
64#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)
65
66/* Bits in VERSION */
67#define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff)
68#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16)
69
70/* Constants for CSRx:BITS */
71#define ATMEL_SPI_BITS_8 0
72#define ATMEL_SPI_BITS_9 1
73#define ATMEL_SPI_BITS_10 2
74#define ATMEL_SPI_BITS_11 3
75#define ATMEL_SPI_BITS_12 4
76#define ATMEL_SPI_BITS_13 5
77#define ATMEL_SPI_BITS_14 6
78#define ATMEL_SPI_BITS_15 7
79#define ATMEL_SPI_BITS_16 8
80
81struct atmel_spi_slave {
Tom Rinie80fa2c2018-04-07 09:15:50 -040082 struct spi_slave slave;
Tom Rini5270df22018-04-07 09:15:06 -040083 void *regs;
84 u32 mr;
85};
Tom Rinie80fa2c2018-04-07 09:15:50 -040086
87static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave)
88{
89 return container_of(slave, struct atmel_spi_slave, slave);
90}
91
92/* Register access macros */
93#define spi_readl(as, reg) \
94 readl(as->regs + ATMEL_SPI_##reg)
95#define spi_writel(as, reg, value) \
96 writel(value, as->regs + ATMEL_SPI_##reg)
97
98#if !defined(CONFIG_SYS_SPI_WRITE_TOUT)
99#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
100#endif