blob: 17a715bac92e9fb840b08b2ae40f28dd81a0711d [file] [log] [blame]
Vikas Manochae66c49f2016-02-11 15:47:20 -08001/*
2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/rcc.h>
11#include <asm/arch/stm32.h>
12#include <asm/arch/stm32_periph.h>
13
14void clock_setup(int peripheral)
15{
16 switch (peripheral) {
17 case USART1_CLOCK_CFG:
18 setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
19 break;
20 case GPIO_A_CLOCK_CFG:
21 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
22 break;
23 case GPIO_B_CLOCK_CFG:
24 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
25 break;
26 case GPIO_C_CLOCK_CFG:
27 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
28 break;
29 case GPIO_D_CLOCK_CFG:
30 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
31 break;
32 case GPIO_E_CLOCK_CFG:
33 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
34 break;
35 case GPIO_F_CLOCK_CFG:
36 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
37 break;
38 case GPIO_G_CLOCK_CFG:
39 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
40 break;
41 case GPIO_H_CLOCK_CFG:
42 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
43 break;
44 case GPIO_I_CLOCK_CFG:
45 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
46 break;
47 case GPIO_J_CLOCK_CFG:
48 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
49 break;
50 case GPIO_K_CLOCK_CFG:
51 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
52 break;
53 default:
54 break;
55 }
56}