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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
3 *
wdenk082acfd2005-01-10 00:01:04 +00004 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
wdenk8ed96042005-01-09 23:16:25 +00005 *
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02006 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +02008 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenk8ed96042005-01-09 23:16:25 +00009 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
wdenk8ed96042005-01-09 23:16:25 +000013 */
14
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020015#include <asm-offsets.h>
wdenk8ed96042005-01-09 23:16:25 +000016#include <config.h>
Kyungmin Park751b9b52008-01-17 16:43:25 +090017
wdenk8ed96042005-01-09 23:16:25 +000018/*
19 *************************************************************************
20 *
21 * Startup Code (reset vector)
22 *
23 * do important init only if we don't start from memory!
24 * setup Memory and board specific bits prior to relocation.
25 * relocate armboot to ram
26 * setup stack
27 *
28 *************************************************************************
29 */
30
Albert ARIBAUD41623c92014-04-15 16:13:51 +020031 .globl reset
Heiko Schochere48b7c02010-09-17 13:10:40 +020032
33reset:
34 /*
35 * set the cpu to SVC32 mode
36 */
37 mrs r0,cpsr
38 bic r0,r0,#0x1f
39 orr r0,r0,#0xd3
40 msr cpsr,r0
41
Heiko Schochere48b7c02010-09-17 13:10:40 +020042 /* the mask ROM code should have PLL and others stable */
43#ifndef CONFIG_SKIP_LOWLEVEL_INIT
44 bl cpu_init_crit
45#endif
46
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000047 bl _main
Heiko Schochere48b7c02010-09-17 13:10:40 +020048
49/*------------------------------------------------------------------------------*/
50
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000051 .globl c_runtime_cpu_setup
52c_runtime_cpu_setup:
Heiko Schochere48b7c02010-09-17 13:10:40 +020053
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000054 bx lr
Heiko Schocherbafe7432010-10-13 07:57:14 +020055
wdenk8ed96042005-01-09 23:16:25 +000056/*
57 *************************************************************************
58 *
59 * CPU_init_critical registers
60 *
61 * setup important registers
62 * setup memory timing
63 *
64 *************************************************************************
65 */
Magnus Lilja40c642b2009-06-13 20:50:01 +020066#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk8ed96042005-01-09 23:16:25 +000067cpu_init_crit:
68 /*
69 * flush v4 I/D caches
70 */
71 mov r0, #0
George G. Davis409a07c2010-05-11 10:15:36 -040072 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
73 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
wdenk8ed96042005-01-09 23:16:25 +000074
75 /*
76 * disable MMU stuff and caches
77 */
78 mrc p15, 0, r0, c1, c0, 0
79 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
80 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
Yuichiro Gotoba10b852016-02-25 10:23:34 +090081 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
wdenk8ed96042005-01-09 23:16:25 +000082 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
wdenk8ed96042005-01-09 23:16:25 +000083 mcr p15, 0, r0, c1, c0, 0
84
85 /*
wdenk082acfd2005-01-10 00:01:04 +000086 * Jump to board specific initialization... The Mask ROM will have already initialized
87 * basic memory. Go here to bump up clock rate and handle wake up conditions.
wdenk8ed96042005-01-09 23:16:25 +000088 */
wdenk082acfd2005-01-10 00:01:04 +000089 mov ip, lr /* persevere link reg across call */
Wolfgang Denk87cb6862005-10-06 17:08:18 +020090 bl lowlevel_init /* go setup pll,mux,memory */
wdenk082acfd2005-01-10 00:01:04 +000091 mov lr, ip /* restore link */
92 mov pc, lr /* back to my caller */
Magnus Lilja40c642b2009-06-13 20:50:01 +020093#endif /* CONFIG_SKIP_LOWLEVEL_INIT */