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wdenk2d5b5612003-10-14 19:43:55 +00001/*
wdenk42d1f032003-10-15 23:53:47 +00002 * include/asm-arm/arch-ixp425/ixp425.h
wdenk2d5b5612003-10-14 19:43:55 +00003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * Register definitions for IXP425
wdenk2d5b5612003-10-14 19:43:55 +00005 *
6 * Copyright (C) 2002 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef _ASM_ARM_IXP425_H_
15#define _ASM_ARM_IXP425_H_
16
17#define BIT(x) (1<<(x))
18
19/* FIXME: Only this does work for u-boot... find out why... [RS] */
20#define UBOOT_REG_FIX 1
21#ifdef UBOOT_REG_FIX
22# undef io_p2v
23# undef __REG
24# ifndef __ASSEMBLY__
25# define io_p2v(PhAdd) (PhAdd)
26# define __REG(x) (*((volatile u32 *)io_p2v(x)))
wdenk42d1f032003-10-15 23:53:47 +000027# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
wdenk2d5b5612003-10-14 19:43:55 +000028# else
wdenk42d1f032003-10-15 23:53:47 +000029# define __REG(x) (x)
wdenk2d5b5612003-10-14 19:43:55 +000030# endif
31#endif /* UBOOT_REG_FIX */
32
33/*
wdenk42d1f032003-10-15 23:53:47 +000034 *
wdenk2d5b5612003-10-14 19:43:55 +000035 * IXP425 Memory map:
36 *
37 * Phy Phy Size Map Size Virt Description
38 * =========================================================================
39 *
wdenk42d1f032003-10-15 23:53:47 +000040 * 0x00000000 0x10000000 SDRAM 1
wdenk2d5b5612003-10-14 19:43:55 +000041 *
42 * 0x10000000 0x10000000 SDRAM 2
43 *
44 * 0x20000000 0x10000000 SDRAM 3
45 *
wdenk42d1f032003-10-15 23:53:47 +000046 * 0x30000000 0x10000000 SDRAM 4
wdenk2d5b5612003-10-14 19:43:55 +000047 *
48 * The above four are aliases to the same memory location (0x00000000)
49 *
50 * 0x48000000 0x4000000 PCI Memory
51 *
52 * 0x50000000 0x10000000 Not Mapped EXP BUS
53 *
54 * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
55 *
wdenk42d1f032003-10-15 23:53:47 +000056 * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
wdenk2d5b5612003-10-14 19:43:55 +000057 *
wdenk42d1f032003-10-15 23:53:47 +000058 * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
wdenk2d5b5612003-10-14 19:43:55 +000059 *
60 * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
61 *
wdenk42d1f032003-10-15 23:53:47 +000062 * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
wdenk2d5b5612003-10-14 19:43:55 +000063 */
64
65/*
66 * SDRAM
67 */
68#define IXP425_SDRAM_BASE (0x00000000)
69#define IXP425_SDRAM_BASE_ALT (0x10000000)
70
71
72/*
73 * PCI Configuration space
74 */
75#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
76#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000)
77#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
78
79/*
80 * Expansion BUS Configuration registers
81 */
82#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
83#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000)
84#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
85
86/*
87 * Peripheral space
88 */
89#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
90#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000)
91#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
92
93/*
94 * SDRAM configuration registers
95 */
96#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
97
wdenk42d1f032003-10-15 23:53:47 +000098/*
wdenk2d5b5612003-10-14 19:43:55 +000099 * Q Manager space .. not static mapped
100 */
101#define IXP425_QMGR_BASE_PHYS (0x60000000)
102#define IXP425_QMGR_BASE_VIRT (0xFFFDE000)
103#define IXP425_QMGR_REGION_SIZE (0x00004000)
104
105/*
106 * Expansion BUS
107 *
108 * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
109 * Exp Bus config registers:
110 *
111 * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
112 * and The expansion bus to IXP425_EXP_BUS_BASE2
113 */
114#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
115#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
116#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000)
117
118#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
119#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT
120
121#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
122#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
123
124#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
125#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
126#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
127#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
128#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
129#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
130#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
131#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
132
133#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000)
134#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000)
135#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000)
136#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000)
137#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000)
138#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000)
139#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000)
140#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000)
141
142#define IXP425_FLASH_WRITABLE (0x2)
143#define IXP425_FLASH_DEFAULT (0xbcd23c40)
144#define IXP425_FLASH_WRITE (0xbcd23c42)
145
146
147#define IXP425_EXP_CS0_OFFSET 0x00
148#define IXP425_EXP_CS1_OFFSET 0x04
149#define IXP425_EXP_CS2_OFFSET 0x08
150#define IXP425_EXP_CS3_OFFSET 0x0C
151#define IXP425_EXP_CS4_OFFSET 0x10
152#define IXP425_EXP_CS5_OFFSET 0x14
153#define IXP425_EXP_CS6_OFFSET 0x18
154#define IXP425_EXP_CS7_OFFSET 0x1C
155#define IXP425_EXP_CFG0_OFFSET 0x20
156#define IXP425_EXP_CFG1_OFFSET 0x24
157#define IXP425_EXP_CFG2_OFFSET 0x28
158#define IXP425_EXP_CFG3_OFFSET 0x2C
159
160/*
161 * Expansion Bus Controller registers.
162 */
163#ifndef __ASSEMBLY__
164#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x)))
165#else
166#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
167#endif
168
169#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
170#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
wdenk42d1f032003-10-15 23:53:47 +0000171#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
wdenk2d5b5612003-10-14 19:43:55 +0000172#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
173#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
174#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
wdenk42d1f032003-10-15 23:53:47 +0000175#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
wdenk2d5b5612003-10-14 19:43:55 +0000176#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
177
wdenk42d1f032003-10-15 23:53:47 +0000178#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
179#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
180#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
wdenk2d5b5612003-10-14 19:43:55 +0000181#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
182
183/*
184 * SDRAM Controller registers.
185 */
186#define IXP425_SDR_CONFIG_OFFSET 0x00
187#define IXP425_SDR_REFRESH_OFFSET 0x04
188#define IXP425_SDR_IR_OFFSET 0x08
189
190#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
191
192#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
193#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
194#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
195
196/*
197 * UART registers
198 */
199#define IXP425_UART1 0
200#define IXP425_UART2 0x1000
201
202#define IXP425_UART_RBR_OFFSET 0x00
203#define IXP425_UART_THR_OFFSET 0x00
204#define IXP425_UART_DLL_OFFSET 0x00
205#define IXP425_UART_IER_OFFSET 0x04
206#define IXP425_UART_DLH_OFFSET 0x04
207#define IXP425_UART_IIR_OFFSET 0x08
208#define IXP425_UART_FCR_OFFSET 0x00
209#define IXP425_UART_LCR_OFFSET 0x0c
210#define IXP425_UART_MCR_OFFSET 0x10
211#define IXP425_UART_LSR_OFFSET 0x14
212#define IXP425_UART_MSR_OFFSET 0x18
213#define IXP425_UART_SPR_OFFSET 0x1c
214#define IXP425_UART_ISR_OFFSET 0x20
215
216#define IXP425_UART_CFG_BASE_PHYS (0xc8000000)
217
218#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
219#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
220#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
221#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
222#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
223#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
224#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
225#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
226#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
227#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
228#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
229#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
230#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
231
232#define IER_DMAE (1 << 7) /* DMA Requests Enable */
233#define IER_UUE (1 << 6) /* UART Unit Enable */
234#define IER_NRZE (1 << 5) /* NRZ coding Enable */
235#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
236#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
237#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
238#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
239#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
240
241#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
242#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
243#define IIR_TOD (1 << 3) /* Time Out Detected */
244#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
245#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
246#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
247
248#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
249#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
250#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
251#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
252#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
253#define FCR_ITL_1 (0)
254#define FCR_ITL_8 (FCR_ITL1)
255#define FCR_ITL_16 (FCR_ITL2)
256#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
257
258#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
259#define LCR_SB (1 << 6) /* Set Break */
260#define LCR_STKYP (1 << 5) /* Sticky Parity */
261#define LCR_EPS (1 << 4) /* Even Parity Select */
262#define LCR_PEN (1 << 3) /* Parity Enable */
263#define LCR_STB (1 << 2) /* Stop Bit */
264#define LCR_WLS1 (1 << 1) /* Word Length Select */
265#define LCR_WLS0 (1 << 0) /* Word Length Select */
266
267#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
268#define LSR_TEMT (1 << 6) /* Transmitter Empty */
269#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
270#define LSR_BI (1 << 4) /* Break Interrupt */
271#define LSR_FE (1 << 3) /* Framing Error */
272#define LSR_PE (1 << 2) /* Parity Error */
273#define LSR_OE (1 << 1) /* Overrun Error */
274#define LSR_DR (1 << 0) /* Data Ready */
275
wdenk42d1f032003-10-15 23:53:47 +0000276#define MCR_LOOP (1 << 4) */
wdenk2d5b5612003-10-14 19:43:55 +0000277#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
278#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
279#define MCR_RTS (1 << 1) /* Request to Send */
280#define MCR_DTR (1 << 0) /* Data Terminal Ready */
281
282#define MSR_DCD (1 << 7) /* Data Carrier Detect */
283#define MSR_RI (1 << 6) /* Ring Indicator */
284#define MSR_DSR (1 << 5) /* Data Set Ready */
285#define MSR_CTS (1 << 4) /* Clear To Send */
286#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
287#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
288#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
289#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
290
291#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT
292#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
293/*
wdenk42d1f032003-10-15 23:53:47 +0000294 * Peripheral Space Registers
wdenk2d5b5612003-10-14 19:43:55 +0000295 */
296#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
297#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
298#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
299#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
300#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
301#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
302#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
303#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
304#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
305#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
306#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
307#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
308
309#define IXP425_UART1_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x0000)
310#define IXP425_UART2_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x1000)
311#define IXP425_PMU_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x2000)
312#define IXP425_INTC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x3000)
313#define IXP425_GPIO_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x4000)
314#define IXP425_TIMER_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x5000)
315#define IXP425_NPEA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x6000)
316#define IXP425_NPEB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x7000)
317#define IXP425_NPEC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x8000)
318#define IXP425_EthA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x9000)
319#define IXP425_EthB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xA000)
320#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000)
321
322
wdenk42d1f032003-10-15 23:53:47 +0000323/*
wdenk2d5b5612003-10-14 19:43:55 +0000324 * UART Register Definitions , Offsets only as there are 2 UARTS.
325 * IXP425_UART1_BASE , IXP425_UART2_BASE.
326 */
327
328#undef UART_NO_RX_INTERRUPT
329
330#define IXP425_UART_XTAL 14745600
331
332/*
333 * Constants to make it easy to access Interrupt Controller registers
334 */
335#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */
336#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */
337#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
338#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */
339#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */
340#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */
341#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
342#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
343
344/*
345 * Interrupt Controller Register Definitions.
346 */
347#ifndef __ASSEMBLY__
348#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x)))
349#else
350#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
351#endif
352
353#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET)
354#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET)
355#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET)
356#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET)
357#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET)
358#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET)
wdenk42d1f032003-10-15 23:53:47 +0000359#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
wdenk2d5b5612003-10-14 19:43:55 +0000360#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET)
wdenk42d1f032003-10-15 23:53:47 +0000361
wdenk2d5b5612003-10-14 19:43:55 +0000362/*
363 * Constants to make it easy to access GPIO registers
364 */
365#define IXP425_GPIO_GPOUTR_OFFSET 0x00
366#define IXP425_GPIO_GPOER_OFFSET 0x04
367#define IXP425_GPIO_GPINR_OFFSET 0x08
368#define IXP425_GPIO_GPISR_OFFSET 0x0C
369#define IXP425_GPIO_GPIT1R_OFFSET 0x10
370#define IXP425_GPIO_GPIT2R_OFFSET 0x14
371#define IXP425_GPIO_GPCLKR_OFFSET 0x18
372#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C
373
wdenk42d1f032003-10-15 23:53:47 +0000374/*
wdenk2d5b5612003-10-14 19:43:55 +0000375 * GPIO Register Definitions.
376 * [Only perform 32bit reads/writes]
377 */
378#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x)))
379
380#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
381#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
382#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
383#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
384#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
385#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
386#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
387#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
388
389/*
390 * Constants to make it easy to access Timer Control/Status registers
391 */
392#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */
393#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
394#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
395#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
396#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
397#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */
398#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */
399#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */
400#define IXP425_OSST_OFFSET 0x20 /* Timer Status */
401
402/*
403 * Operating System Timer Register Definitions.
404 */
405
406#ifndef __ASSEMBLY__
407#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
408#else
409#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
410#endif
411
412#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
413#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
414#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
415#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
416#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
417#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
418#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
419#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
420#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET)
421
422/*
wdenk42d1f032003-10-15 23:53:47 +0000423 * Timer register values and bit definitions
wdenk2d5b5612003-10-14 19:43:55 +0000424 */
425#define IXP425_OST_ENABLE BIT(0)
426#define IXP425_OST_ONE_SHOT BIT(1)
427/* Low order bits of reload value ignored */
wdenk42d1f032003-10-15 23:53:47 +0000428#define IXP425_OST_RELOAD_MASK (0x3)
wdenk2d5b5612003-10-14 19:43:55 +0000429#define IXP425_OST_DISABLED (0x0)
430#define IXP425_OSST_TIMER_1_PEND BIT(0)
431#define IXP425_OSST_TIMER_2_PEND BIT(1)
432#define IXP425_OSST_TIMER_TS_PEND BIT(2)
433#define IXP425_OSST_TIMER_WDOG_PEND BIT(3)
434#define IXP425_OSST_TIMER_WARM_RESET BIT(4)
435
436/*
437 * Constants to make it easy to access PCI Control/Status registers
438 */
439#define PCI_NP_AD_OFFSET 0x00
440#define PCI_NP_CBE_OFFSET 0x04
441#define PCI_NP_WDATA_OFFSET 0x08
442#define PCI_NP_RDATA_OFFSET 0x0c
443#define PCI_CRP_AD_CBE_OFFSET 0x10
444#define PCI_CRP_WDATA_OFFSET 0x14
445#define PCI_CRP_RDATA_OFFSET 0x18
446#define PCI_CSR_OFFSET 0x1c
447#define PCI_ISR_OFFSET 0x20
448#define PCI_INTEN_OFFSET 0x24
449#define PCI_DMACTRL_OFFSET 0x28
450#define PCI_AHBMEMBASE_OFFSET 0x2c
451#define PCI_AHBIOBASE_OFFSET 0x30
452#define PCI_PCIMEMBASE_OFFSET 0x34
453#define PCI_AHBDOORBELL_OFFSET 0x38
454#define PCI_PCIDOORBELL_OFFSET 0x3C
455#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
456#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
457#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
458#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
459#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
460#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
461
462/*
463 * PCI Control/Status Registers
464 */
465#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x)))
466
467#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
468#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
469#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
470#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
471#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
472#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
473#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
wdenk42d1f032003-10-15 23:53:47 +0000474#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
wdenk2d5b5612003-10-14 19:43:55 +0000475#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET)
476#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET)
477#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
478#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
479#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
480#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
481#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
482#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
483#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
484#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
485#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
486#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
487#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
488#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
489
490/*
wdenk42d1f032003-10-15 23:53:47 +0000491 * PCI register values and bit definitions
wdenk2d5b5612003-10-14 19:43:55 +0000492 */
493
494/* CSR bit definitions */
495#define PCI_CSR_HOST BIT(0)
496#define PCI_CSR_ARBEN BIT(1)
497#define PCI_CSR_ADS BIT(2)
498#define PCI_CSR_PDS BIT(3)
499#define PCI_CSR_ABE BIT(4)
500#define PCI_CSR_DBT BIT(5)
501#define PCI_CSR_ASE BIT(8)
502#define PCI_CSR_IC BIT(15)
503
504/* ISR (Interrupt status) Register bit definitions */
505#define PCI_ISR_PSE BIT(0)
506#define PCI_ISR_PFE BIT(1)
507#define PCI_ISR_PPE BIT(2)
508#define PCI_ISR_AHBE BIT(3)
509#define PCI_ISR_APDC BIT(4)
510#define PCI_ISR_PADC BIT(5)
511#define PCI_ISR_ADB BIT(6)
512#define PCI_ISR_PDB BIT(7)
513
514/* INTEN (Interrupt Enable) Register bit definitions */
515#define PCI_INTEN_PSE BIT(0)
516#define PCI_INTEN_PFE BIT(1)
517#define PCI_INTEN_PPE BIT(2)
518#define PCI_INTEN_AHBE BIT(3)
519#define PCI_INTEN_APDC BIT(4)
520#define PCI_INTEN_PADC BIT(5)
521#define PCI_INTEN_ADB BIT(6)
522#define PCI_INTEN_PDB BIT(7)
523
524/*
525 * Shift value for byte enable on NP cmd/byte enable register
526 */
527#define IXP425_PCI_NP_CBE_BESL 4
528
529/*
530 * PCI commands supported by NP access unit
531 */
532#define NP_CMD_IOREAD 0x2
533#define NP_CMD_IOWRITE 0x3
534#define NP_CMD_CONFIGREAD 0xa
535#define NP_CMD_CONFIGWRITE 0xb
536#define NP_CMD_MEMREAD 0x6
537#define NP_CMD_MEMWRITE 0x7
538
539#if 0
540#ifndef __ASSEMBLY__
541extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
542extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
543extern void ixp425_pci_init(void *);
544#endif
545#endif
546
547/*
548 * Constants for CRP access into local config space
549 */
550#define CRP_AD_CBE_BESL 20
551#define CRP_AD_CBE_WRITE BIT(16)
552
553/*
554 * Clock Speed Definitions.
555 */
wdenk42d1f032003-10-15 23:53:47 +0000556#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
wdenk2d5b5612003-10-14 19:43:55 +0000557
558
559#endif