blob: d9a3671b26894f8fb49ae072c3554c3411a3f6c1 [file] [log] [blame]
Stefan Roese029faf32010-04-27 11:37:28 +02001/*
2 * (C) Copyright 2009-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese029faf32010-04-27 11:37:28 +02006 */
7
8/*
9 * icon.h - configuration for Mosaixtech ICON (440SPe)
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 */
18#define CONFIG_ICON 1 /* Board is icon */
Stefan Roese029faf32010-04-27 11:37:28 +020019#define CONFIG_440 1 /* ... PPC440 family */
20#define CONFIG_440SPE 1 /* Specifc SPe support */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021
22#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
23
Stefan Roese029faf32010-04-27 11:37:28 +020024#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
25#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
26
27/*
28 * Include common defines/options for all AMCC eval boards
29 */
30#define CONFIG_HOSTNAME icon
31#include "amcc-common.h"
32
33#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
34#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
35
36/*
37 * Base addresses -- Note these are effective addresses where the
38 * actual resources get mapped (not physical addresses)
39 */
40#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */
Stefan Roese029faf32010-04-27 11:37:28 +020041#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
42
43#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
44#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
45#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
46
47#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
48#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */
49#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
50
51#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
52#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
53#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
54#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
55#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
56#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
57
58/* base address of inbound PCIe window */
59#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
60
61/* System RAM mapped to PCI space */
62#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
63#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
64#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
65
66#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */
67#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4
68#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000
69
70#define CONFIG_SYS_FLASH_SIZE (64 << 20)
71#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
72#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
73#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000
74#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
75 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
76
77/*
78 * Initial RAM & stack pointer (placed in internal SRAM)
79 */
80#define CONFIG_SYS_TEMP_STACK_OCM 1
81#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
82#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020083#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */
Stefan Roese029faf32010-04-27 11:37:28 +020084
Wolfgang Denk553f0982010-10-26 13:32:32 +020085#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020086 GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020087#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese029faf32010-04-27 11:37:28 +020088
89/*
90 * Serial Port
91 */
Stefan Roese550650d2010-09-20 16:05:31 +020092#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese029faf32010-04-27 11:37:28 +020093#undef CONFIG_SYS_EXT_SERIAL_CLOCK
94
95/*
96 * DDR2 SDRAM
97 */
98#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
99#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */
100#define CONFIG_DDR_ECC /* with ECC support */
101#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
102
103/*
104 * I2C
105 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000106#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Stefan Roese029faf32010-04-27 11:37:28 +0200107
Stefan Roese029faf32010-04-27 11:37:28 +0200108#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
109
Stefan Roese029faf32010-04-27 11:37:28 +0200110#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
111#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
112#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
113#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
114
115/* I2C bootstrap EEPROM */
116#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
117#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
118#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
119
120/* I2C RTC */
121#define CONFIG_RTC_M41T11
122#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
123#define CONFIG_SYS_I2C_RTC_ADDR 0x68
124#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
125
126/*
Anatolij Gustschin86caca12010-05-26 10:38:59 +0200127 * Video options
128 */
129#define CONFIG_VIDEO
130
131#ifdef CONFIG_VIDEO
132#define CONFIG_VIDEO_SM501
133#define CONFIG_VIDEO_SM501_32BPP
134#define CONFIG_VIDEO_SM501_PCI
135#define VIDEO_FB_LITTLE_ENDIAN
136#define CONFIG_CFB_CONSOLE
137#define CONFIG_VIDEO_LOGO
138#define CONFIG_CONSOLE_EXTRA_INFO
139#define CONFIG_VGA_AS_SINGLE_DEVICE
140#define CONFIG_VIDEO_SW_CURSOR
141#define CONFIG_VIDEO_BMP_RLE8
142#define CONFIG_SPLASH_SCREEN
143#define CFG_CONSOLE_IS_IN_ENV
144#endif
145
146/*
Stefan Roese029faf32010-04-27 11:37:28 +0200147 * Environment
148 */
149#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
150
151/*
152 * Default environment variables
153 */
154#define CONFIG_EXTRA_ENV_SETTINGS \
155 CONFIG_AMCC_DEF_ENV \
156 CONFIG_AMCC_DEF_ENV_POWERPC \
157 CONFIG_AMCC_DEF_ENV_NOR_UPD \
158 "kernel_addr=fc000000\0" \
159 "fdt_addr=fc1e0000\0" \
160 "ramdisk_addr=fc200000\0" \
161 "pciconfighost=1\0" \
162 "pcie_mode=RP:RP:RP\0" \
163 ""
164
165/*
166 * Commands additional to the ones defined in amcc-common.h
167 */
168#define CONFIG_CMD_CHIP_CONFIG
169#define CONFIG_CMD_DATE
170#define CONFIG_CMD_EXT2
171#define CONFIG_CMD_FAT
172#define CONFIG_CMD_PCI
173#define CONFIG_CMD_SDRAM
174#define CONFIG_CMD_SNTP
Anatolij Gustschin86caca12010-05-26 10:38:59 +0200175#ifdef CONFIG_VIDEO
176#define CONFIG_CMD_BMP
177#endif
Stefan Roese029faf32010-04-27 11:37:28 +0200178
179#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */
180#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
181#define CONFIG_HAS_ETH0
182#define CONFIG_PHY_RESET /* reset phy upon startup */
183#define CONFIG_PHY_RESET_DELAY 1000
184#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */
185#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */
186
187/*
188 * FLASH related
189 */
190#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
191#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
192#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
193#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
194
195#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
196#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */
197#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/
198
199#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
200#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
201
202#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
203#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */
204
205#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
206#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
207#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */
208
209/* Address and size of Redundant Environment Sector */
210#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
211#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
212
213/*
214 * PCI stuff
215 */
216/* General PCI */
217#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000218#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese029faf32010-04-27 11:37:28 +0200219#define CONFIG_PCI_PNP /* do pci plug-and-play */
220#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
221#define CONFIG_PCI_CONFIG_HOST_BRIDGE
222#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/
223
224/* Board-specific PCI */
225#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
226#undef CONFIG_SYS_PCI_MASTER_INIT
227
228#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
229#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
230
231/*
232 * Xilinx System ACE support
233 */
234#define CONFIG_SYSTEMACE /* Enable SystemACE support */
235#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
236#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
237#define CONFIG_DOS_PARTITION
238
239/*
240 * External Bus Controller (EBC) Setup
241 */
242
243/* Memory Bank 0 (Flash) initialization */
244#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
245 EBC_BXAP_TWT_ENCODE(7) | \
246 EBC_BXAP_BCE_DISABLE | \
247 EBC_BXAP_BCT_2TRANS | \
248 EBC_BXAP_CSN_ENCODE(0) | \
249 EBC_BXAP_OEN_ENCODE(0) | \
250 EBC_BXAP_WBN_ENCODE(0) | \
251 EBC_BXAP_WBF_ENCODE(0) | \
252 EBC_BXAP_TH_ENCODE(0) | \
253 EBC_BXAP_RE_DISABLED | \
254 EBC_BXAP_SOR_DELAYED | \
255 EBC_BXAP_BEM_WRITEONLY | \
256 EBC_BXAP_PEN_DISABLED)
257#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
258 EBC_BXCR_BS_64MB | \
259 EBC_BXCR_BU_RW | \
260 EBC_BXCR_BW_16BIT)
261
262/* Memory Bank 1 (Xilinx System ACE controller) initialization */
263#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
264 EBC_BXAP_TWT_ENCODE(4) | \
265 EBC_BXAP_BCE_DISABLE | \
266 EBC_BXAP_BCT_2TRANS | \
267 EBC_BXAP_CSN_ENCODE(0) | \
268 EBC_BXAP_OEN_ENCODE(0) | \
269 EBC_BXAP_WBN_ENCODE(0) | \
270 EBC_BXAP_WBF_ENCODE(0) | \
271 EBC_BXAP_TH_ENCODE(0) | \
272 EBC_BXAP_RE_DISABLED | \
273 EBC_BXAP_SOR_NONDELAYED | \
274 EBC_BXAP_BEM_WRITEONLY | \
275 EBC_BXAP_PEN_DISABLED)
276#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
277 EBC_BXCR_BS_1MB | \
278 EBC_BXCR_BU_RW | \
279 EBC_BXCR_BW_16BIT)
280
281/*
282 * Initialize EBC CONFIG -
283 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
284 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
285 */
286#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
287 EBC_CFG_PTD_ENABLE | \
288 EBC_CFG_RTC_16PERCLK | \
289 EBC_CFG_ATC_PREVIOUS | \
290 EBC_CFG_DTC_PREVIOUS | \
291 EBC_CFG_CTC_PREVIOUS | \
292 EBC_CFG_OEO_PREVIOUS | \
293 EBC_CFG_EMC_DEFAULT | \
294 EBC_CFG_PME_DISABLE | \
295 EBC_CFG_PR_16)
296
297/*
298 * GPIO Setup
299 */
300#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
301#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
302#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
303#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
304
305#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
306 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
307 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
308 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
309#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
310#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
311#define CONFIG_SYS_GPIO_ODR 0
312
313#endif /* __CONFIG_H */