Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 51f660120fa907ac8e393cfe11618e58e356ae1d / . / arch / arm / dts / k3-j721e-r5-sk.dts
blob: abce864fff4794a67cf9cc5255044e258308faf9 [file] [log] [blame]
Sinthu Rajadaad7d62022-02-09 15:06:56 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j721e.dtsi"
9#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
10#include "k3-j721e-ddr.dtsi"
11
12/ {
13 model = "Texas Instruments J721E SK R5";
14
15 aliases {
16 remoteproc0 = &sysctrler;
17 remoteproc1 = &a72_0;
18 };
19
20 chosen {
21 stdout-path = "serial2:115200n8";
22 tick-timer = &timer1;
23 };
24
25 memory@80000000 {
26 device_type = "memory";
27 /* 4G RAM */
28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
29 <0x00000008 0x80000000 0x00000000 0x80000000>;
30 };
31
32 reserved_memory: reserved-memory {
33 #address-cells = <2>;
34 #size-cells = <2>;
35 ranges;
36
37 secure_ddr: optee@9e800000 {
38 reg = <0x00 0x9e800000 0x00 0x01800000>;
39 alignment = <0x1000>;
40 no-map;
41 };
42
43 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x00 0xa0000000 0x00 0x100000>;
46 no-map;
47 };
48
49 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
50 compatible = "shared-dma-pool";
51 reg = <0x00 0xa0100000 0x00 0xf00000>;
52 no-map;
53 };
54
55 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
56 compatible = "shared-dma-pool";
57 reg = <0x00 0xa1000000 0x00 0x100000>;
58 no-map;
59 };
60
61 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
62 compatible = "shared-dma-pool";
63 reg = <0x00 0xa1100000 0x00 0xf00000>;
64 no-map;
65 };
66
67 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
68 compatible = "shared-dma-pool";
69 reg = <0x00 0xa2000000 0x00 0x100000>;
70 no-map;
71 };
72
73 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
74 compatible = "shared-dma-pool";
75 reg = <0x00 0xa2100000 0x00 0xf00000>;
76 no-map;
77 };
78
79 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
80 compatible = "shared-dma-pool";
81 reg = <0x00 0xa3000000 0x00 0x100000>;
82 no-map;
83 };
84
85 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
86 compatible = "shared-dma-pool";
87 reg = <0x00 0xa3100000 0x00 0xf00000>;
88 no-map;
89 };
90
91 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
92 compatible = "shared-dma-pool";
93 reg = <0x00 0xa4000000 0x00 0x100000>;
94 no-map;
95 };
96
97 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
98 compatible = "shared-dma-pool";
99 reg = <0x00 0xa4100000 0x00 0xf00000>;
100 no-map;
101 };
102
103 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
104 compatible = "shared-dma-pool";
105 reg = <0x00 0xa5000000 0x00 0x100000>;
106 no-map;
107 };
108
109 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
110 compatible = "shared-dma-pool";
111 reg = <0x00 0xa5100000 0x00 0xf00000>;
112 no-map;
113 };
114
115 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
116 compatible = "shared-dma-pool";
117 reg = <0x00 0xa6000000 0x00 0x100000>;
118 no-map;
119 };
120
121 c66_0_memory_region: c66-memory@a6100000 {
122 compatible = "shared-dma-pool";
123 reg = <0x00 0xa6100000 0x00 0xf00000>;
124 no-map;
125 };
126
127 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
128 compatible = "shared-dma-pool";
129 reg = <0x00 0xa7000000 0x00 0x100000>;
130 no-map;
131 };
132
133 c66_1_memory_region: c66-memory@a7100000 {
134 compatible = "shared-dma-pool";
135 reg = <0x00 0xa7100000 0x00 0xf00000>;
136 no-map;
137 };
138
139 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
140 compatible = "shared-dma-pool";
141 reg = <0x00 0xa8000000 0x00 0x100000>;
142 no-map;
143 };
144
145 c71_0_memory_region: c71-memory@a8100000 {
146 compatible = "shared-dma-pool";
147 reg = <0x00 0xa8100000 0x00 0xf00000>;
148 no-map;
149 };
150
151 rtos_ipc_memory_region: ipc-memories@aa000000 {
152 reg = <0x00 0xaa000000 0x00 0x01c00000>;
153 alignment = <0x1000>;
154 no-map;
155 };
156 };
157
158 a72_0: a72@0 {
159 compatible = "ti,am654-rproc";
160 reg = <0x0 0x00a90000 0x0 0x10>;
161 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
162 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
163 resets = <&k3_reset 202 0>;
164 clocks = <&k3_clks 61 1>;
165 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
166 assigned-clock-rates = <2000000000>, <200000000>;
167 ti,sci = <&dmsc>;
168 ti,sci-proc-id = <32>;
169 ti,sci-host-id = <10>;
170 u-boot,dm-spl;
171 };
172
173 clk_200mhz: dummy_clock_200mhz {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <200000000>;
177 u-boot,dm-spl;
178 };
179
180 clk_19_2mhz: dummy_clock_19_2mhz {
181 compatible = "fixed-clock";
182 #clock-cells = <0>;
183 clock-frequency = <19200000>;
184 u-boot,dm-spl;
185 };
186};
187
188&cbass_mcu_wakeup {
189 mcu_secproxy: secproxy@28380000 {
190 u-boot,dm-spl;
191 compatible = "ti,am654-secure-proxy";
192 reg = <0x0 0x2a380000 0x0 0x80000>,
193 <0x0 0x2a400000 0x0 0x80000>,
194 <0x0 0x2a480000 0x0 0x80000>;
195 reg-names = "rt", "scfg", "target_data";
196 #mbox-cells = <1>;
197 };
198
199 sysctrler: sysctrler {
200 u-boot,dm-spl;
201 compatible = "ti,am654-system-controller";
202 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
203 mbox-names = "tx", "rx";
204 };
205
206 wkup_vtm0: wkup_vtm@42040000 {
207 compatible = "ti,am654-vtm", "ti,j721e-avs";
208 reg = <0x0 0x42040000 0x0 0x330>;
209 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
210 #thermal-sensor-cells = <1>;
211 };
212
213 dm_tifs: dm-tifs {
214 compatible = "ti,j721e-dm-sci";
215 ti,host-id = <3>;
216 ti,secure-host;
217 mbox-names = "rx", "tx";
218 mboxes= <&mcu_secproxy 21>,
219 <&mcu_secproxy 23>;
220 u-boot,dm-spl;
221 };
222};
223
224&cbass_main {
225 main_esm: esm@700000 {
226 compatible = "ti,j721e-esm";
227 reg = <0x0 0x700000 0x0 0x1000>;
228 ti,esm-pins = <344>, <345>;
229 u-boot,dm-spl;
230 };
231};
232
233&dmsc {
234 mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
235 mbox-names = "tx", "rx", "notify";
236 ti,host-id = <4>;
237 ti,secure-host;
238};
239
240&wkup_pmx0 {
241 wkup_uart0_pins_default: wkup_uart0_pins_default {
242 u-boot,dm-spl;
243 pinctrl-single,pins = <
244 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
245 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
246 >;
247 };
248
249 mcu_uart0_pins_default: mcu_uart0_pins_default {
250 u-boot,dm-spl;
251 pinctrl-single,pins = <
252 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
253 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
254 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
255 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
256 >;
257 };
258
259 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
260 pinctrl-single,pins = <
261 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
262 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
263 >;
264 };
265
266 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
267 pinctrl-single,pins = <
268 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
269 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
270 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
271 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
272 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
273 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
274 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
275 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
276 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
277 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
278 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
279 >;
280 };
281
282 mcu_i2c0_pins_default: mcu_i2c0_pins_default {
283 pinctrl-single,pins = <
284 J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
285 J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
286 >;
287 };
288};
289
290&main_pmx0 {
291 main_uart0_pins_default: main_uart0_pins_default {
292 u-boot,dm-spl;
293 pinctrl-single,pins = <
294 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
295 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
296 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
297 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
298 >;
299 };
300
301 main_usbss0_pins_default: main_usbss0_pins_default {
302 pinctrl-single,pins = <
303 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
304 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
305 >;
306 };
307
308 main_usbss1_pins_default: main-usbss1-pins-default {
309 pinctrl-single,pins = <
310 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
311 >;
312 };
313
314 main_mmc1_pins_default: main_mmc1_pins_default {
315 pinctrl-single,pins = <
316 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
317 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
318 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
319 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
320 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
321 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
322 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
323 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
324 >;
325 };
326
327 main_i2c0_pins_default: main-i2c0-pins-default {
328 pinctrl-single,pins = <
329 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
330 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
331 >;
332 };
333
334 main_i2c1_pins_default: main-i2c1-pins-default {
335 pinctrl-single,pins = <
336 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
337 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
338 >;
339 };
340
341 main_i2c2_pins_default: main-i2c2-pins-default {
342 pinctrl-single,pins = <
343 J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */
344 J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */
345 >;
346 };
347
348 main_i2c3_pins_default: main-i2c3-pins-default {
349 pinctrl-single,pins = <
350 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
351 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
352 >;
353 };
354
355 main_i2c5_pins_default: main-i2c5-pins-default {
356 pinctrl-single,pins = <
357 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
358 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
359 >;
360 };
361};
362
363&wkup_uart0 {
364 u-boot,dm-spl;
365 pinctrl-names = "default";
366 pinctrl-0 = <&wkup_uart0_pins_default>;
367 status = "okay";
368};
369
370&mcu_uart0 {
371 /delete-property/ power-domains;
372 /delete-property/ clocks;
373 /delete-property/ clock-names;
374 pinctrl-names = "default";
375 pinctrl-0 = <&mcu_uart0_pins_default>;
376 status = "okay";
377 clock-frequency = <48000000>;
378};
379
380&main_uart0 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&main_uart0_pins_default>;
383 status = "okay";
384 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
385};
386
387&main_sdhci0 {
388 status = "disabled";
389};
390
391&main_sdhci1 {
392 /delete-property/ power-domains;
393 /delete-property/ assigned-clocks;
394 /delete-property/ assigned-clock-parents;
395 pinctrl-names = "default";
396 pinctrl-0 = <&main_mmc1_pins_default>;
397 clock-names = "clk_xin";
398 clocks = <&clk_200mhz>;
399 ti,driver-strength-ohm = <50>;
400};
401
402&wkup_i2c0 {
403 u-boot,dm-spl;
404 tps659412: tps659412@48 {
405 reg = <0x48>;
406 compatible = "ti,tps659412";
407 u-boot,dm-spl;
408 pinctrl-names = "default";
409 pinctrl-0 = <&wkup_i2c0_pins_default>;
410 clock-frequency = <400000>;
411
412 regulators: regulators {
413 u-boot,dm-spl;
414 /* 3 Phase Buck */
415 buck123_reg: buck123 {
416 /* VDD_CPU */
417 regulator-name = "buck123";
418 regulator-min-microvolt = <800000>;
419 regulator-max-microvolt = <1250000>;
420 regulator-always-on;
421 regulator-boot-on;
422 u-boot,dm-spl;
423 };
424 };
425 };
426};
427
428&wkup_vtm0 {
429 vdd-supply-2 = <&buck123_reg>;
430 u-boot,dm-spl;
431};
432
433&usbss0 {
434 /delete-property/ power-domains;
435 /delete-property/ assigned-clocks;
436 /delete-property/ assigned-clock-parents;
437 clocks = <&clk_19_2mhz>;
438 clock-names = "usb2_refclk";
439 pinctrl-names = "default";
440 pinctrl-0 = <&main_usbss0_pins_default>;
441 ti,vbus-divider;
442};
443
444&usbss1 {
445 /delete-property/ power-domains;
446 /delete-property/ assigned-clocks;
447 /delete-property/ assigned-clock-parents;
448 clocks = <&clk_19_2mhz>;
449 clock-names = "usb2_refclk";
450 pinctrl-names = "default";
451 pinctrl-0 = <&main_usbss1_pins_default>;
452};
453
454&main_i2c0 {
455 pinctrl-names = "default";
456 pinctrl-0 = <&main_i2c0_pins_default>;
457 clock-frequency = <400000>;
458};
459
460&ospi0 {
461 pinctrl-names = "default";
462 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
463
464 reg = <0x0 0x47040000 0x0 0x100>,
465 <0x0 0x50000000 0x0 0x8000000>;
466
467 flash@0{
468 compatible = "jedec,spi-nor";
469 reg = <0x0>;
470 spi-tx-bus-width = <8>;
471 spi-rx-bus-width = <8>;
472 spi-max-frequency = <25000000>;
473 cdns,tshsl-ns = <60>;
474 cdns,tsd2d-ns = <60>;
475 cdns,tchsh-ns = <60>;
476 cdns,tslch-ns = <60>;
477 cdns,read-delay = <4>;
478 cdns,phy-mode;
479 #address-cells = <1>;
480 #size-cells = <1>;
481 };
482};
483
484&ospi1 {
485 status = "disabled";
486};
487
488&mcu_ringacc {
489 ti,sci = <&dm_tifs>;
490};
491
492&mcu_udmap {
493 ti,sci = <&dm_tifs>;
494};
495
496&mailbox0_cluster0 {
497 interrupts = <436>;
498
499 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
500 ti,mbox-rx = <0 0 0>;
501 ti,mbox-tx = <1 0 0>;
502 };
503
504 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
505 ti,mbox-rx = <2 0 0>;
506 ti,mbox-tx = <3 0 0>;
507 };
508};
509
510&mailbox0_cluster1 {
511 interrupts = <432>;
512
513 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
514 ti,mbox-rx = <0 0 0>;
515 ti,mbox-tx = <1 0 0>;
516 };
517
518 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
519 ti,mbox-rx = <2 0 0>;
520 ti,mbox-tx = <3 0 0>;
521 };
522};
523
524&mailbox0_cluster2 {
525 interrupts = <428>;
526
527 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
528 ti,mbox-rx = <0 0 0>;
529 ti,mbox-tx = <1 0 0>;
530 };
531
532 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
533 ti,mbox-rx = <2 0 0>;
534 ti,mbox-tx = <3 0 0>;
535 };
536};
537
538&mailbox0_cluster3 {
539 interrupts = <424>;
540
541 mbox_c66_0: mbox-c66-0 {
542 ti,mbox-rx = <0 0 0>;
543 ti,mbox-tx = <1 0 0>;
544 };
545
546 mbox_c66_1: mbox-c66-1 {
547 ti,mbox-rx = <2 0 0>;
548 ti,mbox-tx = <3 0 0>;
549 };
550};
551
552&mailbox0_cluster4 {
553 interrupts = <420>;
554
555 mbox_c71_0: mbox-c71-0 {
556 ti,mbox-rx = <0 0 0>;
557 ti,mbox-tx = <1 0 0>;
558 };
559};
560
561&mailbox0_cluster5 {
562 status = "disabled";
563};
564
565&mailbox0_cluster6 {
566 status = "disabled";
567};
568
569&mailbox0_cluster7 {
570 status = "disabled";
571};
572
573&mailbox0_cluster8 {
574 status = "disabled";
575};
576
577&mailbox0_cluster9 {
578 status = "disabled";
579};
580
581&mailbox0_cluster10 {
582 status = "disabled";
583};
584
585&mailbox0_cluster11 {
586 status = "disabled";
587};
588
589&mcu_r5fss0_core0 {
590 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
591 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
592 <&mcu_r5fss0_core0_memory_region>;
593};
594
595&mcu_r5fss0_core1 {
596 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
597 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
598 <&mcu_r5fss0_core1_memory_region>;
599};
600
601&main_r5fss0_core0 {
602 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
603 memory-region = <&main_r5fss0_core0_dma_memory_region>,
604 <&main_r5fss0_core0_memory_region>;
605};
606
607&main_r5fss0_core1 {
608 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
609 memory-region = <&main_r5fss0_core1_dma_memory_region>,
610 <&main_r5fss0_core1_memory_region>;
611};
612
613&main_r5fss1_core0 {
614 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
615 memory-region = <&main_r5fss1_core0_dma_memory_region>,
616 <&main_r5fss1_core0_memory_region>;
617};
618
619&main_r5fss1_core1 {
620 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
621 memory-region = <&main_r5fss1_core1_dma_memory_region>,
622 <&main_r5fss1_core1_memory_region>;
623};
624
625&c66_0 {
626 mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
627 memory-region = <&c66_0_dma_memory_region>,
628 <&c66_0_memory_region>;
629};
630
631&c66_1 {
632 mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
633 memory-region = <&c66_1_dma_memory_region>,
634 <&c66_1_memory_region>;
635};
636
637&c71_0 {
638 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
639 memory-region = <&c71_0_dma_memory_region>,
640 <&c71_0_memory_region>;
641};
642
643/* EEPROM might be read before SYSFW is available */
644&wkup_i2c0 {
645 /delete-property/ power-domains;
646};