Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 8 | #include <asm/io.h> |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 9 | #include <cpu_func.h> |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 10 | #include <malloc.h> |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 11 | #include <miiphy.h> |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 12 | #include <net.h> |
Ben Warren | 10efa02 | 2008-08-31 20:37:00 -0700 | [diff] [blame] | 13 | #include <netdev.h> |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 14 | #include <pci.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 15 | #include <linux/delay.h> |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 16 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 17 | /* Ethernet chip registers. */ |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 18 | #define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */ |
| 19 | #define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */ |
| 20 | #define SCB_CMD 2 /* Rx/Command Unit Command *Word* */ |
| 21 | #define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */ |
| 22 | #define SCB_POINTER 4 /* General purpose pointer. */ |
| 23 | #define SCB_PORT 8 /* Misc. commands and operands. */ |
| 24 | #define SCB_FLASH 12 /* Flash memory control. */ |
| 25 | #define SCB_EEPROM 14 /* EEPROM memory control. */ |
| 26 | #define SCB_CTRL_MDI 16 /* MDI interface control. */ |
| 27 | #define SCB_EARLY_RX 20 /* Early receive byte count. */ |
| 28 | #define SCB_GEN_CONTROL 28 /* 82559 General Control Register */ |
| 29 | #define SCB_GEN_STATUS 29 /* 82559 General Status register */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 30 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 31 | /* 82559 SCB status word defnitions */ |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 32 | #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ |
| 33 | #define SCB_STATUS_FR 0x4000 /* frame received */ |
| 34 | #define SCB_STATUS_CNA 0x2000 /* CU left active state */ |
| 35 | #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ |
| 36 | #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ |
| 37 | #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ |
| 38 | #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 39 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 40 | #define SCB_INTACK_MASK 0xFD00 /* all the above */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 41 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 42 | #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) |
| 43 | #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 44 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 45 | /* System control block commands */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 46 | /* CU Commands */ |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 47 | #define CU_NOP 0x0000 |
| 48 | #define CU_START 0x0010 |
| 49 | #define CU_RESUME 0x0020 |
| 50 | #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ |
| 51 | #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ |
| 52 | #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ |
| 53 | #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 54 | |
| 55 | /* RUC Commands */ |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 56 | #define RUC_NOP 0x0000 |
| 57 | #define RUC_START 0x0001 |
| 58 | #define RUC_RESUME 0x0002 |
| 59 | #define RUC_ABORT 0x0004 |
| 60 | #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ |
| 61 | #define RUC_RESUMENR 0x0007 |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 62 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 63 | #define CU_CMD_MASK 0x00f0 |
| 64 | #define RU_CMD_MASK 0x0007 |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 65 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 66 | #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ |
| 67 | #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 68 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 69 | #define CU_STATUS_MASK 0x00C0 |
| 70 | #define RU_STATUS_MASK 0x003C |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 71 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 72 | #define RU_STATUS_IDLE (0 << 2) |
| 73 | #define RU_STATUS_SUS (1 << 2) |
| 74 | #define RU_STATUS_NORES (2 << 2) |
| 75 | #define RU_STATUS_READY (4 << 2) |
| 76 | #define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2)) |
| 77 | #define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2)) |
| 78 | #define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2)) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 79 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 80 | /* 82559 Port interface commands. */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 81 | #define I82559_RESET 0x00000000 /* Software reset */ |
| 82 | #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ |
| 83 | #define I82559_SELECTIVE_RESET 0x00000002 |
| 84 | #define I82559_DUMP 0x00000003 |
| 85 | #define I82559_DUMP_WAKEUP 0x00000007 |
| 86 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 87 | /* 82559 Eeprom interface. */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 88 | #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ |
| 89 | #define EE_CS 0x02 /* EEPROM chip select. */ |
| 90 | #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ |
| 91 | #define EE_WRITE_0 0x01 |
| 92 | #define EE_WRITE_1 0x05 |
| 93 | #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ |
| 94 | #define EE_ENB (0x4800 | EE_CS) |
| 95 | #define EE_CMD_BITS 3 |
| 96 | #define EE_DATA_BITS 16 |
| 97 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 98 | /* The EEPROM commands include the alway-set leading bit. */ |
Marek Vasut | a6c06ec | 2020-05-23 16:23:28 +0200 | [diff] [blame] | 99 | #define EE_EWENB_CMD(addr_len) (4 << (addr_len)) |
| 100 | #define EE_WRITE_CMD(addr_len) (5 << (addr_len)) |
| 101 | #define EE_READ_CMD(addr_len) (6 << (addr_len)) |
| 102 | #define EE_ERASE_CMD(addr_len) (7 << (addr_len)) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 103 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 104 | /* Receive frame descriptors. */ |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 105 | struct eepro100_rxfd { |
Marek Vasut | d47cf87 | 2020-05-23 15:02:47 +0200 | [diff] [blame] | 106 | u16 status; |
| 107 | u16 control; |
| 108 | u32 link; /* struct eepro100_rxfd * */ |
| 109 | u32 rx_buf_addr; /* void * */ |
| 110 | u32 count; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 111 | |
Marek Vasut | d47cf87 | 2020-05-23 15:02:47 +0200 | [diff] [blame] | 112 | u8 data[PKTSIZE_ALIGN]; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | #define RFD_STATUS_C 0x8000 /* completion of received frame */ |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 116 | #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 117 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 118 | #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ |
| 119 | #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ |
| 120 | #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ |
| 121 | #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 122 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 123 | #define RFD_COUNT_MASK 0x3fff |
| 124 | #define RFD_COUNT_F 0x4000 |
| 125 | #define RFD_COUNT_EOF 0x8000 |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 126 | |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 127 | #define RFD_RX_CRC 0x0800 /* crc error */ |
| 128 | #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ |
| 129 | #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ |
| 130 | #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ |
| 131 | #define RFD_RX_SHORT 0x0080 /* short frame error */ |
| 132 | #define RFD_RX_LENGTH 0x0020 |
| 133 | #define RFD_RX_ERROR 0x0010 /* receive error */ |
| 134 | #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ |
| 135 | #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ |
| 136 | #define RFD_RX_TCO 0x0001 /* TCO indication */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 137 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 138 | /* Transmit frame descriptors */ |
Marek Vasut | d47cf87 | 2020-05-23 15:02:47 +0200 | [diff] [blame] | 139 | struct eepro100_txfd { /* Transmit frame descriptor set. */ |
| 140 | u16 status; |
| 141 | u16 command; |
| 142 | u32 link; /* void * */ |
| 143 | u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ |
| 144 | s32 count; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 145 | |
Marek Vasut | d47cf87 | 2020-05-23 15:02:47 +0200 | [diff] [blame] | 146 | u32 tx_buf_addr0; /* void *, frame to be transmitted. */ |
| 147 | s32 tx_buf_size0; /* Length of Tx frame. */ |
| 148 | u32 tx_buf_addr1; /* void *, frame to be transmitted. */ |
| 149 | s32 tx_buf_size1; /* Length of Tx frame. */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 150 | }; |
| 151 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 152 | #define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */ |
| 153 | #define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ |
| 154 | #define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ |
| 155 | #define TXCB_CMD_I 0x2000 /* generate interrupt on completion */ |
| 156 | #define TXCB_CMD_S 0x4000 /* suspend on completion */ |
| 157 | #define TXCB_CMD_EL 0x8000 /* last command block in CBL */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 158 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 159 | #define TXCB_COUNT_MASK 0x3fff |
| 160 | #define TXCB_COUNT_EOF 0x8000 |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 161 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 162 | /* The Speedo3 Rx and Tx frame/buffer descriptors. */ |
Marek Vasut | d47cf87 | 2020-05-23 15:02:47 +0200 | [diff] [blame] | 163 | struct descriptor { /* A generic descriptor. */ |
| 164 | u16 status; |
| 165 | u16 command; |
| 166 | u32 link; /* struct descriptor * */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 167 | |
| 168 | unsigned char params[0]; |
| 169 | }; |
| 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_CMD_EL 0x8000 |
| 172 | #define CONFIG_SYS_CMD_SUSPEND 0x4000 |
| 173 | #define CONFIG_SYS_CMD_INT 0x2000 |
| 174 | #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ |
| 175 | #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 176 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_STATUS_C 0x8000 |
| 178 | #define CONFIG_SYS_STATUS_OK 0x2000 |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 179 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 180 | /* Misc. */ |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 181 | #define NUM_RX_DESC PKTBUFSRX |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 182 | #define NUM_TX_DESC 1 /* Number of TX descriptors */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 183 | |
| 184 | #define TOUT_LOOP 1000000 |
| 185 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 186 | static struct eepro100_rxfd rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ |
| 187 | static struct eepro100_txfd tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 188 | static int rx_next; /* RX descriptor ring pointer */ |
| 189 | static int tx_next; /* TX descriptor ring pointer */ |
| 190 | static int tx_threshold; |
| 191 | |
| 192 | /* |
| 193 | * The parameters for a CmdConfigure operation. |
| 194 | * There are so many options that it would be difficult to document |
| 195 | * each bit. We mostly use the default or recommended settings. |
| 196 | */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 197 | static const char i82558_config_cmd[] = { |
| 198 | 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ |
| 199 | 0, 0x2E, 0, 0x60, 0x08, 0x88, |
| 200 | 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ |
| 201 | 0x31, 0x05, |
| 202 | }; |
| 203 | |
Marek Vasut | bd159c6 | 2020-05-23 16:49:07 +0200 | [diff] [blame^] | 204 | struct eepro100_priv { |
| 205 | struct eth_device dev; |
| 206 | }; |
| 207 | |
Wolfgang Denk | 03b0040 | 2014-10-21 15:23:32 +0200 | [diff] [blame] | 208 | #if defined(CONFIG_E500) |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 209 | #define bus_to_phys(dev, a) (a) |
| 210 | #define phys_to_bus(dev, a) (a) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 211 | #else |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 212 | #define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a)) |
| 213 | #define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a)) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 214 | #endif |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 215 | |
Marek Vasut | acdf5d8 | 2020-05-23 16:27:37 +0200 | [diff] [blame] | 216 | static int INW(struct eth_device *dev, u_long addr) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 217 | { |
Marek Vasut | 81bdeea | 2020-05-23 14:14:45 +0200 | [diff] [blame] | 218 | return le16_to_cpu(readw(addr + (void *)dev->iobase)); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Marek Vasut | acdf5d8 | 2020-05-23 16:27:37 +0200 | [diff] [blame] | 221 | static void OUTW(struct eth_device *dev, int command, u_long addr) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 222 | { |
Marek Vasut | 81bdeea | 2020-05-23 14:14:45 +0200 | [diff] [blame] | 223 | writew(cpu_to_le16(command), addr + (void *)dev->iobase); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 224 | } |
| 225 | |
Marek Vasut | acdf5d8 | 2020-05-23 16:27:37 +0200 | [diff] [blame] | 226 | static void OUTL(struct eth_device *dev, int command, u_long addr) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 227 | { |
Marek Vasut | 81bdeea | 2020-05-23 14:14:45 +0200 | [diff] [blame] | 228 | writel(cpu_to_le32(command), addr + (void *)dev->iobase); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 229 | } |
| 230 | |
Jon Loeliger | 07d38a1 | 2007-07-09 17:30:01 -0500 | [diff] [blame] | 231 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
Marek Vasut | acdf5d8 | 2020-05-23 16:27:37 +0200 | [diff] [blame] | 232 | static int INL(struct eth_device *dev, u_long addr) |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 233 | { |
Marek Vasut | 81bdeea | 2020-05-23 14:14:45 +0200 | [diff] [blame] | 234 | return le32_to_cpu(readl(addr + (void *)dev->iobase)); |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 235 | } |
| 236 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 237 | static int get_phyreg(struct eth_device *dev, unsigned char addr, |
Marek Vasut | 773af83 | 2020-05-23 13:21:43 +0200 | [diff] [blame] | 238 | unsigned char reg, unsigned short *value) |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 239 | { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 240 | int cmd; |
| 241 | int timeout = 50; |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 242 | |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 243 | /* read requested data */ |
| 244 | cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 245 | OUTL(dev, cmd, SCB_CTRL_MDI); |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 246 | |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 247 | do { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 248 | udelay(1000); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 249 | cmd = INL(dev, SCB_CTRL_MDI); |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 250 | } while (!(cmd & (1 << 28)) && (--timeout)); |
| 251 | |
| 252 | if (timeout == 0) |
| 253 | return -1; |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 254 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 255 | *value = (unsigned short)(cmd & 0xffff); |
Wolfgang Denk | c570b2f | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 256 | |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 257 | return 0; |
| 258 | } |
| 259 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 260 | static int set_phyreg(struct eth_device *dev, unsigned char addr, |
Marek Vasut | 773af83 | 2020-05-23 13:21:43 +0200 | [diff] [blame] | 261 | unsigned char reg, unsigned short value) |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 262 | { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 263 | int cmd; |
| 264 | int timeout = 50; |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 265 | |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 266 | /* write requested data */ |
| 267 | cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 268 | OUTL(dev, cmd | value, SCB_CTRL_MDI); |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 269 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 270 | while (!(INL(dev, SCB_CTRL_MDI) & (1 << 28)) && (--timeout)) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 271 | udelay(1000); |
| 272 | |
| 273 | if (timeout == 0) |
| 274 | return -1; |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 275 | |
| 276 | return 0; |
| 277 | } |
Wolfgang Denk | a912733 | 2005-09-26 00:39:59 +0200 | [diff] [blame] | 278 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 279 | /* |
| 280 | * Check if given phyaddr is valid, i.e. there is a PHY connected. |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 281 | * Do this by checking model value field from ID2 register. |
| 282 | */ |
Marek Vasut | 7a30873 | 2020-05-23 13:23:13 +0200 | [diff] [blame] | 283 | static struct eth_device *verify_phyaddr(const char *devname, |
Marek Vasut | 773af83 | 2020-05-23 13:21:43 +0200 | [diff] [blame] | 284 | unsigned char addr) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 285 | { |
| 286 | struct eth_device *dev; |
| 287 | unsigned short value; |
| 288 | unsigned char model; |
| 289 | |
| 290 | dev = eth_get_dev_by_name(devname); |
Marek Vasut | b013173 | 2020-05-23 13:45:41 +0200 | [diff] [blame] | 291 | if (!dev) { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 292 | printf("%s: no such device\n", devname); |
| 293 | return NULL; |
| 294 | } |
| 295 | |
| 296 | /* read id2 register */ |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 297 | if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 298 | printf("%s: mii read timeout!\n", devname); |
| 299 | return NULL; |
| 300 | } |
| 301 | |
| 302 | /* get model */ |
| 303 | model = (unsigned char)((value >> 4) & 0x003f); |
| 304 | |
| 305 | if (model == 0) { |
| 306 | printf("%s: no PHY at address %d\n", devname, addr); |
| 307 | return NULL; |
| 308 | } |
| 309 | |
| 310 | return dev; |
| 311 | } |
| 312 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 313 | static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad, |
| 314 | int reg) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 315 | { |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 316 | unsigned short value = 0; |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 317 | struct eth_device *dev; |
| 318 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 319 | dev = verify_phyaddr(bus->name, addr); |
Marek Vasut | b013173 | 2020-05-23 13:45:41 +0200 | [diff] [blame] | 320 | if (!dev) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 321 | return -1; |
| 322 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 323 | if (get_phyreg(dev, addr, reg, &value) != 0) { |
| 324 | printf("%s: mii read timeout!\n", bus->name); |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 325 | return -1; |
| 326 | } |
| 327 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 328 | return value; |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 329 | } |
| 330 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 331 | static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad, |
| 332 | int reg, u16 value) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 333 | { |
| 334 | struct eth_device *dev; |
| 335 | |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 336 | dev = verify_phyaddr(bus->name, addr); |
Marek Vasut | b013173 | 2020-05-23 13:45:41 +0200 | [diff] [blame] | 337 | if (!dev) |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 338 | return -1; |
| 339 | |
| 340 | if (set_phyreg(dev, addr, reg, value) != 0) { |
Joe Hershberger | 5a49f17 | 2016-08-08 11:28:38 -0500 | [diff] [blame] | 341 | printf("%s: mii write timeout!\n", bus->name); |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 342 | return -1; |
| 343 | } |
| 344 | |
| 345 | return 0; |
| 346 | } |
| 347 | |
Jon Loeliger | 07d38a1 | 2007-07-09 17:30:01 -0500 | [diff] [blame] | 348 | #endif |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 349 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 350 | static void init_rx_ring(struct eth_device *dev) |
| 351 | { |
| 352 | int i; |
| 353 | |
| 354 | for (i = 0; i < NUM_RX_DESC; i++) { |
| 355 | rx_ring[i].status = 0; |
| 356 | rx_ring[i].control = (i == NUM_RX_DESC - 1) ? |
| 357 | cpu_to_le16 (RFD_CONTROL_S) : 0; |
| 358 | rx_ring[i].link = |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 359 | cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv, |
| 360 | (u32)&rx_ring[(i + 1) % |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 361 | NUM_RX_DESC])); |
| 362 | rx_ring[i].rx_buf_addr = 0xffffffff; |
| 363 | rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16); |
| 364 | } |
| 365 | |
| 366 | flush_dcache_range((unsigned long)rx_ring, |
| 367 | (unsigned long)rx_ring + |
| 368 | (sizeof(*rx_ring) * NUM_RX_DESC)); |
| 369 | |
| 370 | rx_next = 0; |
| 371 | } |
| 372 | |
| 373 | static void purge_tx_ring(struct eth_device *dev) |
| 374 | { |
| 375 | tx_next = 0; |
| 376 | tx_threshold = 0x01208000; |
| 377 | memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC); |
| 378 | |
| 379 | flush_dcache_range((unsigned long)tx_ring, |
| 380 | (unsigned long)tx_ring + |
| 381 | (sizeof(*tx_ring) * NUM_TX_DESC)); |
| 382 | } |
| 383 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 384 | /* Wait for the chip get the command. */ |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 385 | static int wait_for_eepro100(struct eth_device *dev) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 386 | { |
| 387 | int i; |
| 388 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 389 | for (i = 0; INW(dev, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) { |
Marek Vasut | 9b12ff9 | 2020-05-23 13:20:14 +0200 | [diff] [blame] | 390 | if (i >= TOUT_LOOP) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 391 | return 0; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | return 1; |
| 395 | } |
| 396 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 397 | static int eepro100_txcmd_send(struct eth_device *dev, |
| 398 | struct eepro100_txfd *desc) |
| 399 | { |
| 400 | u16 rstat; |
| 401 | int i = 0; |
| 402 | |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 403 | flush_dcache_range((unsigned long)desc, |
| 404 | (unsigned long)desc + sizeof(*desc)); |
| 405 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 406 | if (!wait_for_eepro100(dev)) |
| 407 | return -ETIMEDOUT; |
| 408 | |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 409 | OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, (u32)desc), SCB_POINTER); |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 410 | OUTW(dev, SCB_M | CU_START, SCB_CMD); |
| 411 | |
| 412 | while (true) { |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 413 | invalidate_dcache_range((unsigned long)desc, |
| 414 | (unsigned long)desc + sizeof(*desc)); |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 415 | rstat = le16_to_cpu(desc->status); |
| 416 | if (rstat & CONFIG_SYS_STATUS_C) |
| 417 | break; |
| 418 | |
| 419 | if (i++ >= TOUT_LOOP) { |
| 420 | printf("%s: Tx error buffer not ready\n", dev->name); |
| 421 | return -EINVAL; |
| 422 | } |
| 423 | } |
| 424 | |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 425 | invalidate_dcache_range((unsigned long)desc, |
| 426 | (unsigned long)desc + sizeof(*desc)); |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 427 | rstat = le16_to_cpu(desc->status); |
| 428 | |
| 429 | if (!(rstat & CONFIG_SYS_STATUS_OK)) { |
| 430 | printf("TX error status = 0x%08X\n", rstat); |
| 431 | return -EIO; |
| 432 | } |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 437 | /* SROM Read. */ |
| 438 | static int read_eeprom(struct eth_device *dev, int location, int addr_len) |
| 439 | { |
| 440 | unsigned short retval = 0; |
Marek Vasut | a6c06ec | 2020-05-23 16:23:28 +0200 | [diff] [blame] | 441 | int read_cmd = location | EE_READ_CMD(addr_len); |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 442 | int i; |
| 443 | |
| 444 | OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM); |
| 445 | OUTW(dev, EE_ENB, SCB_EEPROM); |
| 446 | |
| 447 | /* Shift the read command bits out. */ |
| 448 | for (i = 12; i >= 0; i--) { |
| 449 | short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; |
| 450 | |
| 451 | OUTW(dev, EE_ENB | dataval, SCB_EEPROM); |
| 452 | udelay(1); |
| 453 | OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM); |
| 454 | udelay(1); |
| 455 | } |
| 456 | OUTW(dev, EE_ENB, SCB_EEPROM); |
| 457 | |
| 458 | for (i = 15; i >= 0; i--) { |
| 459 | OUTW(dev, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM); |
| 460 | udelay(1); |
| 461 | retval = (retval << 1) | |
| 462 | ((INW(dev, SCB_EEPROM) & EE_DATA_READ) ? 1 : 0); |
| 463 | OUTW(dev, EE_ENB, SCB_EEPROM); |
| 464 | udelay(1); |
| 465 | } |
| 466 | |
| 467 | /* Terminate the EEPROM access. */ |
| 468 | OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM); |
| 469 | return retval; |
| 470 | } |
| 471 | |
Marek Vasut | 66fed73 | 2020-05-23 16:20:25 +0200 | [diff] [blame] | 472 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
| 473 | static int eepro100_initialize_mii(struct eth_device *dev) |
| 474 | { |
| 475 | /* register mii command access routines */ |
| 476 | struct mii_dev *mdiodev; |
| 477 | int ret; |
| 478 | |
| 479 | mdiodev = mdio_alloc(); |
| 480 | if (!mdiodev) |
| 481 | return -ENOMEM; |
| 482 | |
| 483 | strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); |
| 484 | mdiodev->read = eepro100_miiphy_read; |
| 485 | mdiodev->write = eepro100_miiphy_write; |
| 486 | |
| 487 | ret = mdio_register(mdiodev); |
| 488 | if (ret < 0) { |
| 489 | mdio_free(mdiodev); |
| 490 | return ret; |
| 491 | } |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | #else |
| 496 | static int eepro100_initialize_mii(struct eth_device *dev) |
| 497 | { |
| 498 | return 0; |
| 499 | } |
| 500 | #endif |
| 501 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 502 | static struct pci_device_id supported[] = { |
Marek Vasut | 3a15684 | 2020-05-23 15:11:30 +0200 | [diff] [blame] | 503 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557) }, |
| 504 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559) }, |
| 505 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER) }, |
| 506 | { } |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 507 | }; |
| 508 | |
| 509 | static void read_hw_addr(struct eth_device *dev, bd_t *bis) |
| 510 | { |
| 511 | u16 sum = 0; |
| 512 | int i, j; |
| 513 | int addr_len = read_eeprom(dev, 0, 6) == 0xffff ? 8 : 6; |
| 514 | |
| 515 | for (j = 0, i = 0; i < 0x40; i++) { |
| 516 | u16 value = read_eeprom(dev, i, addr_len); |
| 517 | |
| 518 | sum += value; |
| 519 | if (i < 3) { |
| 520 | dev->enetaddr[j++] = value; |
| 521 | dev->enetaddr[j++] = value >> 8; |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | if (sum != 0xBABA) { |
| 526 | memset(dev->enetaddr, 0, ETH_ALEN); |
| 527 | debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n", |
| 528 | dev->name, sum); |
| 529 | } |
| 530 | } |
| 531 | |
Marek Vasut | 7a30873 | 2020-05-23 13:23:13 +0200 | [diff] [blame] | 532 | static int eepro100_init(struct eth_device *dev, bd_t *bis) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 533 | { |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 534 | struct eepro100_txfd *ias_cmd, *cfg_cmd; |
| 535 | int ret, status = -1; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 536 | int tx_cur; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 537 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 538 | /* Reset the ethernet controller */ |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 539 | OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT); |
Simon Glass | 07e1114 | 2020-05-10 11:40:10 -0600 | [diff] [blame] | 540 | udelay(20); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 541 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 542 | OUTL(dev, I82559_RESET, SCB_PORT); |
Simon Glass | 07e1114 | 2020-05-10 11:40:10 -0600 | [diff] [blame] | 543 | udelay(20); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 544 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 545 | if (!wait_for_eepro100(dev)) { |
| 546 | printf("Error: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 547 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 548 | } |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 549 | OUTL(dev, 0, SCB_POINTER); |
| 550 | OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 551 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 552 | if (!wait_for_eepro100(dev)) { |
| 553 | printf("Error: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 554 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 555 | } |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 556 | OUTL(dev, 0, SCB_POINTER); |
| 557 | OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 558 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 559 | /* Initialize Rx and Tx rings. */ |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 560 | init_rx_ring(dev); |
| 561 | purge_tx_ring(dev); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 562 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 563 | /* Tell the adapter where the RX ring is located. */ |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 564 | if (!wait_for_eepro100(dev)) { |
| 565 | printf("Error: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 566 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 567 | } |
| 568 | |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 569 | /* RX ring cache was already flushed in init_rx_ring() */ |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 570 | OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, (u32)&rx_ring[rx_next]), |
| 571 | SCB_POINTER); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 572 | OUTW(dev, SCB_M | RUC_START, SCB_CMD); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 573 | |
| 574 | /* Send the Configure frame */ |
| 575 | tx_cur = tx_next; |
| 576 | tx_next = ((tx_next + 1) % NUM_TX_DESC); |
| 577 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 578 | cfg_cmd = &tx_ring[tx_cur]; |
Marek Vasut | b013173 | 2020-05-23 13:45:41 +0200 | [diff] [blame] | 579 | cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND | |
| 580 | CONFIG_SYS_CMD_CONFIGURE); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 581 | cfg_cmd->status = 0; |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 582 | cfg_cmd->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv, |
| 583 | (u32)&tx_ring[tx_next])); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 584 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 585 | memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd, |
Marek Vasut | 773af83 | 2020-05-23 13:21:43 +0200 | [diff] [blame] | 586 | sizeof(i82558_config_cmd)); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 587 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 588 | ret = eepro100_txcmd_send(dev, cfg_cmd); |
| 589 | if (ret) { |
| 590 | if (ret == -ETIMEDOUT) |
| 591 | printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 592 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 593 | } |
| 594 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 595 | /* Send the Individual Address Setup frame */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 596 | tx_cur = tx_next; |
| 597 | tx_next = ((tx_next + 1) % NUM_TX_DESC); |
| 598 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 599 | ias_cmd = &tx_ring[tx_cur]; |
Marek Vasut | b013173 | 2020-05-23 13:45:41 +0200 | [diff] [blame] | 600 | ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND | |
| 601 | CONFIG_SYS_CMD_IAS); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 602 | ias_cmd->status = 0; |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 603 | ias_cmd->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv, |
| 604 | (u32)&tx_ring[tx_next])); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 605 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 606 | memcpy(((struct descriptor *)ias_cmd)->params, dev->enetaddr, 6); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 607 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 608 | ret = eepro100_txcmd_send(dev, ias_cmd); |
| 609 | if (ret) { |
| 610 | if (ret == -ETIMEDOUT) |
| 611 | printf("Error: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 612 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 613 | } |
| 614 | |
Ben Warren | 422b1a0 | 2008-01-09 18:15:53 -0500 | [diff] [blame] | 615 | status = 0; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 616 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 617 | done: |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 618 | return status; |
| 619 | } |
| 620 | |
Joe Hershberger | bccbe61 | 2012-05-21 14:45:25 +0000 | [diff] [blame] | 621 | static int eepro100_send(struct eth_device *dev, void *packet, int length) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 622 | { |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 623 | struct eepro100_txfd *desc; |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 624 | int ret, status = -1; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 625 | int tx_cur; |
| 626 | |
| 627 | if (length <= 0) { |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 628 | printf("%s: bad packet size: %d\n", dev->name, length); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 629 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | tx_cur = tx_next; |
| 633 | tx_next = (tx_next + 1) % NUM_TX_DESC; |
| 634 | |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 635 | desc = &tx_ring[tx_cur]; |
| 636 | desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF | |
| 637 | TXCB_CMD_S | TXCB_CMD_EL); |
| 638 | desc->status = 0; |
| 639 | desc->count = cpu_to_le32(tx_threshold); |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 640 | desc->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv, |
| 641 | (u32)&tx_ring[tx_next])); |
| 642 | desc->tx_desc_addr = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv, |
| 643 | (u32)&desc->tx_buf_addr0)); |
| 644 | desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv, |
| 645 | (u_long)packet)); |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 646 | desc->tx_buf_size0 = cpu_to_le32(length); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 647 | |
Marek Vasut | 95655b9 | 2020-05-23 14:30:31 +0200 | [diff] [blame] | 648 | ret = eepro100_txcmd_send(dev, &tx_ring[tx_cur]); |
| 649 | if (ret) { |
| 650 | if (ret == -ETIMEDOUT) |
| 651 | printf("%s: Tx error ethernet controller not ready.\n", |
| 652 | dev->name); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 653 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | status = length; |
| 657 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 658 | done: |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 659 | return status; |
| 660 | } |
| 661 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 662 | static int eepro100_recv(struct eth_device *dev) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 663 | { |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 664 | struct eepro100_rxfd *desc; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 665 | int rx_prev, length = 0; |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 666 | u16 status, stat; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 667 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 668 | stat = INW(dev, SCB_STATUS); |
| 669 | OUTW(dev, stat & SCB_STATUS_RNR, SCB_STATUS); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 670 | |
| 671 | for (;;) { |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 672 | desc = &rx_ring[rx_next]; |
| 673 | invalidate_dcache_range((unsigned long)desc, |
| 674 | (unsigned long)desc + sizeof(*desc)); |
| 675 | status = le16_to_cpu(desc->status); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 676 | |
Marek Vasut | 9b12ff9 | 2020-05-23 13:20:14 +0200 | [diff] [blame] | 677 | if (!(status & RFD_STATUS_C)) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 678 | break; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 679 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 680 | /* Valid frame status. */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 681 | if ((status & RFD_STATUS_OK)) { |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 682 | /* A valid frame received. */ |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 683 | length = le32_to_cpu(desc->count) & 0x3fff; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 684 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 685 | /* Pass the packet up to the protocol layers. */ |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 686 | net_process_received_packet((u8 *)desc->data, length); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 687 | } else { |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 688 | /* There was an error. */ |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 689 | printf("RX error status = 0x%08X\n", status); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 690 | } |
| 691 | |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 692 | desc->control = cpu_to_le16(RFD_CONTROL_S); |
| 693 | desc->status = 0; |
| 694 | desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16); |
| 695 | flush_dcache_range((unsigned long)desc, |
| 696 | (unsigned long)desc + sizeof(*desc)); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 697 | |
| 698 | rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 699 | desc = &rx_ring[rx_prev]; |
| 700 | desc->control = 0; |
| 701 | flush_dcache_range((unsigned long)desc, |
| 702 | (unsigned long)desc + sizeof(*desc)); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 703 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 704 | /* Update entry information. */ |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 705 | rx_next = (rx_next + 1) % NUM_RX_DESC; |
| 706 | } |
| 707 | |
| 708 | if (stat & SCB_STATUS_RNR) { |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 709 | printf("%s: Receiver is not ready, restart it !\n", dev->name); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 710 | |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 711 | /* Reinitialize Rx ring. */ |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 712 | init_rx_ring(dev); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 713 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 714 | if (!wait_for_eepro100(dev)) { |
| 715 | printf("Error: Can not restart ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 716 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 717 | } |
| 718 | |
Marek Vasut | 5116aae | 2020-05-23 14:55:26 +0200 | [diff] [blame] | 719 | /* RX ring cache was already flushed in init_rx_ring() */ |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 720 | OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, |
| 721 | (u32)&rx_ring[rx_next]), SCB_POINTER); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 722 | OUTW(dev, SCB_M | RUC_START, SCB_CMD); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 723 | } |
| 724 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 725 | done: |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 726 | return length; |
| 727 | } |
| 728 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 729 | static void eepro100_halt(struct eth_device *dev) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 730 | { |
Marek Vasut | aba283d | 2020-05-23 12:49:16 +0200 | [diff] [blame] | 731 | /* Reset the ethernet controller */ |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 732 | OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT); |
Simon Glass | 07e1114 | 2020-05-10 11:40:10 -0600 | [diff] [blame] | 733 | udelay(20); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 734 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 735 | OUTL(dev, I82559_RESET, SCB_PORT); |
Simon Glass | 07e1114 | 2020-05-10 11:40:10 -0600 | [diff] [blame] | 736 | udelay(20); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 737 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 738 | if (!wait_for_eepro100(dev)) { |
| 739 | printf("Error: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 740 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 741 | } |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 742 | OUTL(dev, 0, SCB_POINTER); |
| 743 | OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 744 | |
Marek Vasut | db9f181 | 2020-05-23 13:17:03 +0200 | [diff] [blame] | 745 | if (!wait_for_eepro100(dev)) { |
| 746 | printf("Error: Can not reset ethernet controller.\n"); |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 747 | goto done; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 748 | } |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 749 | OUTL(dev, 0, SCB_POINTER); |
| 750 | OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 751 | |
Marek Vasut | f3878f5 | 2020-05-23 13:52:50 +0200 | [diff] [blame] | 752 | done: |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 753 | return; |
| 754 | } |
| 755 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 756 | int eepro100_initialize(bd_t *bis) |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 757 | { |
Marek Vasut | bd159c6 | 2020-05-23 16:49:07 +0200 | [diff] [blame^] | 758 | struct eepro100_priv *priv; |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 759 | struct eth_device *dev; |
Marek Vasut | 66fed73 | 2020-05-23 16:20:25 +0200 | [diff] [blame] | 760 | int card_number = 0; |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 761 | u32 iobase, status; |
Marek Vasut | 66fed73 | 2020-05-23 16:20:25 +0200 | [diff] [blame] | 762 | pci_dev_t devno; |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 763 | int idx = 0; |
Marek Vasut | 66fed73 | 2020-05-23 16:20:25 +0200 | [diff] [blame] | 764 | int ret; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 765 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 766 | while (1) { |
| 767 | /* Find PCI device */ |
| 768 | devno = pci_find_devices(supported, idx++); |
| 769 | if (devno < 0) |
| 770 | break; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 771 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 772 | pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); |
| 773 | iobase &= ~0xf; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 774 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 775 | debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", |
| 776 | iobase); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 777 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 778 | pci_write_config_dword(devno, PCI_COMMAND, |
| 779 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 780 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 781 | /* Check if I/O accesses and Bus Mastering are enabled. */ |
| 782 | pci_read_config_dword(devno, PCI_COMMAND, &status); |
| 783 | if (!(status & PCI_COMMAND_MEMORY)) { |
| 784 | printf("Error: Can not enable MEM access.\n"); |
| 785 | continue; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 786 | } |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 787 | |
| 788 | if (!(status & PCI_COMMAND_MASTER)) { |
| 789 | printf("Error: Can not enable Bus Mastering.\n"); |
| 790 | continue; |
| 791 | } |
| 792 | |
Marek Vasut | bd159c6 | 2020-05-23 16:49:07 +0200 | [diff] [blame^] | 793 | priv = calloc(1, sizeof(*priv)); |
| 794 | if (!priv) { |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 795 | printf("eepro100: Can not allocate memory\n"); |
| 796 | break; |
| 797 | } |
Marek Vasut | bd159c6 | 2020-05-23 16:49:07 +0200 | [diff] [blame^] | 798 | dev = &priv->dev; |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 799 | |
| 800 | sprintf(dev->name, "i82559#%d", card_number); |
| 801 | dev->priv = (void *)devno; /* this have to come before bus_to_phys() */ |
Marek Vasut | fa9e121 | 2020-05-23 16:38:41 +0200 | [diff] [blame] | 802 | dev->iobase = bus_to_phys(devno, iobase); |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 803 | dev->init = eepro100_init; |
| 804 | dev->halt = eepro100_halt; |
| 805 | dev->send = eepro100_send; |
| 806 | dev->recv = eepro100_recv; |
| 807 | |
| 808 | eth_register(dev); |
| 809 | |
Marek Vasut | 66fed73 | 2020-05-23 16:20:25 +0200 | [diff] [blame] | 810 | ret = eepro100_initialize_mii(dev); |
| 811 | if (ret) { |
| 812 | eth_unregister(dev); |
Marek Vasut | bd159c6 | 2020-05-23 16:49:07 +0200 | [diff] [blame^] | 813 | free(priv); |
Marek Vasut | 66fed73 | 2020-05-23 16:20:25 +0200 | [diff] [blame] | 814 | return ret; |
| 815 | } |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 816 | |
| 817 | card_number++; |
| 818 | |
| 819 | /* Set the latency timer for value. */ |
| 820 | pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); |
| 821 | |
| 822 | udelay(10 * 1000); |
| 823 | |
| 824 | read_hw_addr(dev, bis); |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 825 | } |
| 826 | |
Marek Vasut | 047a800 | 2020-05-23 15:07:30 +0200 | [diff] [blame] | 827 | return card_number; |
wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 828 | } |