blob: d45d5532cafa625c4cd600699d350f3e67e03642 [file] [log] [blame]
Angelo Dureghellob5867b12019-03-13 21:46:41 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
4 */
5
6/ {
7 compatible = "fsl,mcf5249";
8
9 aliases {
10 serial0 = &uart0;
11 };
12
13 soc {
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 mbar: mbar@10000000 {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges = <0x00000000 0x10000000 0x10000>;
23 reg = <0x10000000 0x10000>;
24
25 uart0: uart@1c0 {
26 compatible = "fsl,mcf-uart";
27 reg = <0x1c0 0x40>;
28 status = "disabled";
29 };
30
31 uart1: uart@200 {
32 compatible = "fsl,mcf-uart";
33 reg = <0x200 0x40>;
34 status = "disabled";
35 };
Angelo Dureghello96283b82023-04-05 00:59:27 +020036
37 i2c0: i2c@280 {
38 compatible = "fsl-i2c";
39 #address-cells=<1>;
40 #size-cells=<0>;
41 cell-index = <0>;
42 reg = <0x280 0x14>;
43 clock-frequency = <100000>;
44 status = "disabled";
45 };
46 };
47
48 mbar2: mbar2@80000000 {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges = <0x00000000 0x80000000 0x10000>;
53 reg = <0x80000000 0x10000>;
54
55 i2c1: i2c@440 {
56 compatible = "fsl-i2c";
57 #address-cells=<1>;
58 #size-cells=<0>;
59 cell-index = <0>;
60 reg = <0x440 0x14>;
61 clock-frequency = <100000>;
62 status = "disabled";
63 };
Angelo Dureghellob5867b12019-03-13 21:46:41 +010064 };
65 };
66};