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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese10e8bf82014-11-07 12:37:49 +01002/*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
Stefan Roese10e8bf82014-11-07 12:37:49 +01005 */
6
7#include <common.h>
Simon Goldschmidt64c7c8c2019-11-20 22:27:31 +01008#include <clk.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Vignesh Raghavendra0f247842019-12-05 15:46:06 +053010#include <asm-generic/io.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010011#include <dm.h>
12#include <fdtdec.h>
13#include <malloc.h>
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +010014#include <reset.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010015#include <spi.h>
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053016#include <spi-mem.h>
Simon Glass336d4612020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070018#include <linux/err.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090019#include <linux/errno.h>
Vignesh Raghavendraffab2122020-01-27 10:36:40 +053020#include <linux/sizes.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010021#include "cadence_qspi.h"
22
23#define CQSPI_STIG_READ 0
24#define CQSPI_STIG_WRITE 1
Vignesh Raghavendraffab2122020-01-27 10:36:40 +053025#define CQSPI_READ 2
26#define CQSPI_WRITE 3
Stefan Roese10e8bf82014-11-07 12:37:49 +010027
Stefan Roese10e8bf82014-11-07 12:37:49 +010028static int cadence_spi_write_speed(struct udevice *bus, uint hz)
29{
Simon Glass0fd3d912020-12-22 19:30:28 -070030 struct cadence_spi_plat *plat = dev_get_plat(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +010031 struct cadence_spi_priv *priv = dev_get_priv(bus);
32
33 cadence_qspi_apb_config_baudrate_div(priv->regbase,
Simon Goldschmidt64c7c8c2019-11-20 22:27:31 +010034 plat->ref_clk_hz, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +010035
36 /* Reconfigure delay timing if speed is changed. */
Simon Goldschmidt64c7c8c2019-11-20 22:27:31 +010037 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
Stefan Roese10e8bf82014-11-07 12:37:49 +010038 plat->tshsl_ns, plat->tsd2d_ns,
39 plat->tchsh_ns, plat->tslch_ns);
40
41 return 0;
42}
43
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053044static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
45{
46 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
47 SPI_MEM_OP_NO_ADDR,
48 SPI_MEM_OP_NO_DUMMY,
49 SPI_MEM_OP_DATA_IN(len, idcode, 1));
50
51 return cadence_qspi_apb_command_read(reg_base, &op);
52}
53
Stefan Roese10e8bf82014-11-07 12:37:49 +010054/* Calibration sequence to determine the read data capture delay register */
Chin Liang See98fbd712015-10-17 08:31:55 -050055static int spi_calibration(struct udevice *bus, uint hz)
Stefan Roese10e8bf82014-11-07 12:37:49 +010056{
Stefan Roese10e8bf82014-11-07 12:37:49 +010057 struct cadence_spi_priv *priv = dev_get_priv(bus);
58 void *base = priv->regbase;
Stefan Roese10e8bf82014-11-07 12:37:49 +010059 unsigned int idcode = 0, temp = 0;
60 int err = 0, i, range_lo = -1, range_hi = -1;
61
62 /* start with slowest clock (1 MHz) */
63 cadence_spi_write_speed(bus, 1000000);
64
65 /* configure the read data capture delay register to 0 */
66 cadence_qspi_apb_readdata_capture(base, 1, 0);
67
68 /* Enable QSPI */
69 cadence_qspi_apb_controller_enable(base);
70
71 /* read the ID which will be our golden value */
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053072 err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
Stefan Roese10e8bf82014-11-07 12:37:49 +010073 if (err) {
74 puts("SF: Calibration failed (read)\n");
75 return err;
76 }
77
78 /* use back the intended clock and find low range */
Chin Liang See98fbd712015-10-17 08:31:55 -050079 cadence_spi_write_speed(bus, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +010080 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
81 /* Disable QSPI */
82 cadence_qspi_apb_controller_disable(base);
83
84 /* reconfigure the read data capture delay register */
85 cadence_qspi_apb_readdata_capture(base, 1, i);
86
87 /* Enable back QSPI */
88 cadence_qspi_apb_controller_enable(base);
89
90 /* issue a RDID to get the ID value */
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053091 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
Stefan Roese10e8bf82014-11-07 12:37:49 +010092 if (err) {
93 puts("SF: Calibration failed (read)\n");
94 return err;
95 }
96
97 /* search for range lo */
98 if (range_lo == -1 && temp == idcode) {
99 range_lo = i;
100 continue;
101 }
102
103 /* search for range hi */
104 if (range_lo != -1 && temp != idcode) {
105 range_hi = i - 1;
106 break;
107 }
108 range_hi = i;
109 }
110
111 if (range_lo == -1) {
112 puts("SF: Calibration failed (low range)\n");
113 return err;
114 }
115
116 /* Disable QSPI for subsequent initialization */
117 cadence_qspi_apb_controller_disable(base);
118
119 /* configure the final value for read data capture delay register */
120 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
121 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
122 (range_hi + range_lo) / 2, range_lo, range_hi);
123
124 /* just to ensure we do once only when speed or chip select change */
Chin Liang See98fbd712015-10-17 08:31:55 -0500125 priv->qspi_calibrated_hz = hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100126 priv->qspi_calibrated_cs = spi_chip_select(bus);
127
128 return 0;
129}
130
131static int cadence_spi_set_speed(struct udevice *bus, uint hz)
132{
Simon Glass0fd3d912020-12-22 19:30:28 -0700133 struct cadence_spi_plat *plat = dev_get_plat(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100134 struct cadence_spi_priv *priv = dev_get_priv(bus);
135 int err;
136
Chin Liang See4e609b62015-10-17 08:32:38 -0500137 if (hz > plat->max_hz)
138 hz = plat->max_hz;
139
Stefan Roese10e8bf82014-11-07 12:37:49 +0100140 /* Disable QSPI */
141 cadence_qspi_apb_controller_disable(priv->regbase);
142
Chin Liang See98fbd712015-10-17 08:31:55 -0500143 /*
144 * Calibration required for different current SCLK speed, requested
145 * SCLK speed or chip select
146 */
147 if (priv->previous_hz != hz ||
148 priv->qspi_calibrated_hz != hz ||
Stefan Roese10e8bf82014-11-07 12:37:49 +0100149 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
Chin Liang See98fbd712015-10-17 08:31:55 -0500150 err = spi_calibration(bus, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100151 if (err)
152 return err;
Chin Liang See98fbd712015-10-17 08:31:55 -0500153
154 /* prevent calibration run when same as previous request */
155 priv->previous_hz = hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100156 }
157
158 /* Enable QSPI */
159 cadence_qspi_apb_controller_enable(priv->regbase);
160
161 debug("%s: speed=%d\n", __func__, hz);
162
163 return 0;
164}
165
166static int cadence_spi_probe(struct udevice *bus)
167{
Simon Glass0fd3d912020-12-22 19:30:28 -0700168 struct cadence_spi_plat *plat = dev_get_plat(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100169 struct cadence_spi_priv *priv = dev_get_priv(bus);
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530170 struct clk clk;
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100171 int ret;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100172
173 priv->regbase = plat->regbase;
174 priv->ahbbase = plat->ahbbase;
175
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530176 if (plat->ref_clk_hz == 0) {
177 ret = clk_get_by_index(bus, 0, &clk);
178 if (ret) {
179#ifdef CONFIG_CQSPI_REF_CLK
180 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
181#else
182 return ret;
183#endif
184 } else {
185 plat->ref_clk_hz = clk_get_rate(&clk);
186 clk_free(&clk);
187 if (IS_ERR_VALUE(plat->ref_clk_hz))
188 return plat->ref_clk_hz;
189 }
190 }
191
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100192 ret = reset_get_bulk(bus, &priv->resets);
193 if (ret)
194 dev_warn(bus, "Can't get reset: %d\n", ret);
195 else
196 reset_deassert_bulk(&priv->resets);
197
Stefan Roese10e8bf82014-11-07 12:37:49 +0100198 if (!priv->qspi_is_init) {
199 cadence_qspi_apb_controller_init(plat);
200 priv->qspi_is_init = 1;
201 }
202
203 return 0;
204}
205
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100206static int cadence_spi_remove(struct udevice *dev)
207{
208 struct cadence_spi_priv *priv = dev_get_priv(dev);
209
210 return reset_release_bulk(&priv->resets);
211}
212
Stefan Roese10e8bf82014-11-07 12:37:49 +0100213static int cadence_spi_set_mode(struct udevice *bus, uint mode)
214{
Simon Glass0fd3d912020-12-22 19:30:28 -0700215 struct cadence_spi_plat *plat = dev_get_plat(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100216 struct cadence_spi_priv *priv = dev_get_priv(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100217
218 /* Disable QSPI */
219 cadence_qspi_apb_controller_disable(priv->regbase);
220
221 /* Set SPI mode */
Phil Edworthy7d403f22016-11-29 12:58:31 +0000222 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100223
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530224 /* Enable Direct Access Controller */
225 if (plat->use_dac_mode)
226 cadence_qspi_apb_dac_mode_enable(priv->regbase);
227
Stefan Roese10e8bf82014-11-07 12:37:49 +0100228 /* Enable QSPI */
229 cadence_qspi_apb_controller_enable(priv->regbase);
230
231 return 0;
232}
233
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530234static int cadence_spi_mem_exec_op(struct spi_slave *spi,
235 const struct spi_mem_op *op)
Stefan Roese10e8bf82014-11-07 12:37:49 +0100236{
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530237 struct udevice *bus = spi->dev->parent;
Simon Glass0fd3d912020-12-22 19:30:28 -0700238 struct cadence_spi_plat *plat = dev_get_plat(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100239 struct cadence_spi_priv *priv = dev_get_priv(bus);
240 void *base = priv->regbase;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100241 int err = 0;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530242 u32 mode;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100243
244 /* Set Chip select */
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530245 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
Jason Rush15a70a52018-01-23 17:13:09 -0600246 plat->is_decoded_cs);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100247
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530248 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
249 if (!op->addr.nbytes)
250 mode = CQSPI_STIG_READ;
251 else
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530252 mode = CQSPI_READ;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530253 } else {
254 if (!op->addr.nbytes || !op->data.buf.out)
255 mode = CQSPI_STIG_WRITE;
256 else
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530257 mode = CQSPI_WRITE;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530258 }
Stefan Roese10e8bf82014-11-07 12:37:49 +0100259
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530260 switch (mode) {
261 case CQSPI_STIG_READ:
262 err = cadence_qspi_apb_command_read(base, op);
263 break;
264 case CQSPI_STIG_WRITE:
265 err = cadence_qspi_apb_command_write(base, op);
266 break;
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530267 case CQSPI_READ:
268 err = cadence_qspi_apb_read_setup(plat, op);
269 if (!err)
270 err = cadence_qspi_apb_read_execute(plat, op);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100271 break;
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530272 case CQSPI_WRITE:
273 err = cadence_qspi_apb_write_setup(plat, op);
274 if (!err)
275 err = cadence_qspi_apb_write_execute(plat, op);
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530276 break;
277 default:
278 err = -1;
279 break;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100280 }
281
282 return err;
283}
284
Simon Glassd1998a92020-12-03 16:55:21 -0700285static int cadence_spi_of_to_plat(struct udevice *bus)
Stefan Roese10e8bf82014-11-07 12:37:49 +0100286{
Simon Glass0fd3d912020-12-22 19:30:28 -0700287 struct cadence_spi_plat *plat = dev_get_plat(bus);
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200288 ofnode subnode;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100289
Ley Foon Tan6c353672018-05-07 17:42:55 +0800290 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530291 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
292 &plat->ahbsize);
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200293 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
294 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
295 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
296 plat->trigger_address = dev_read_u32_default(bus,
297 "cdns,trigger-address",
298 0);
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530299 /* Use DAC mode only when MMIO window is at least 8M wide */
300 if (plat->ahbsize >= SZ_8M)
301 plat->use_dac_mode = true;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100302
Stefan Roese10e8bf82014-11-07 12:37:49 +0100303 /* All other paramters are embedded in the child node */
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200304 subnode = dev_read_first_subnode(bus);
305 if (!ofnode_valid(subnode)) {
Stefan Roese10e8bf82014-11-07 12:37:49 +0100306 printf("Error: subnode with SPI flash config missing!\n");
307 return -ENODEV;
308 }
309
Chin Liang See040f4ba2015-10-17 08:32:14 -0500310 /* Use 500 KHz as a suitable default */
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200311 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
312 500000);
Chin Liang See040f4ba2015-10-17 08:32:14 -0500313
Stefan Roese10e8bf82014-11-07 12:37:49 +0100314 /* Read other parameters from DT */
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200315 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
316 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
317 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
318 200);
319 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
320 255);
321 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
322 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100323
324 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
325 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
326 plat->page_size);
327
328 return 0;
329}
330
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530331static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
332 .exec_op = cadence_spi_mem_exec_op,
333};
334
Stefan Roese10e8bf82014-11-07 12:37:49 +0100335static const struct dm_spi_ops cadence_spi_ops = {
Stefan Roese10e8bf82014-11-07 12:37:49 +0100336 .set_speed = cadence_spi_set_speed,
337 .set_mode = cadence_spi_set_mode,
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530338 .mem_ops = &cadence_spi_mem_ops,
Stefan Roese10e8bf82014-11-07 12:37:49 +0100339 /*
340 * cs_info is not needed, since we require all chip selects to be
341 * in the device tree explicitly
342 */
343};
344
345static const struct udevice_id cadence_spi_ids[] = {
Simon Goldschmidt2a3a9992018-11-02 11:54:51 +0100346 { .compatible = "cdns,qspi-nor" },
Vignesh Raghavendradaa94052019-12-05 15:46:07 +0530347 { .compatible = "ti,am654-ospi" },
Stefan Roese10e8bf82014-11-07 12:37:49 +0100348 { }
349};
350
351U_BOOT_DRIVER(cadence_spi) = {
352 .name = "cadence_spi",
353 .id = UCLASS_SPI,
354 .of_match = cadence_spi_ids,
355 .ops = &cadence_spi_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700356 .of_to_plat = cadence_spi_of_to_plat,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700357 .plat_auto = sizeof(struct cadence_spi_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700358 .priv_auto = sizeof(struct cadence_spi_priv),
Stefan Roese10e8bf82014-11-07 12:37:49 +0100359 .probe = cadence_spi_probe,
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100360 .remove = cadence_spi_remove,
361 .flags = DM_FLAG_OS_PREPARE,
Stefan Roese10e8bf82014-11-07 12:37:49 +0100362};