Andy Yan | d1dcf85 | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
| 3 | * Author: Andy Yan <andy.yan@rock-chips.com> |
Philipp Tomsich | ddfe77d | 2017-06-22 23:47:11 +0200 | [diff] [blame^] | 4 | * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
Andy Yan | d1dcf85 | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0 |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <clk-uclass.h> |
| 10 | #include <dm.h> |
| 11 | #include <errno.h> |
| 12 | #include <syscon.h> |
| 13 | #include <asm/arch/clock.h> |
| 14 | #include <asm/arch/cru_rk3368.h> |
| 15 | #include <asm/arch/hardware.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <dm/lists.h> |
| 18 | #include <dt-bindings/clock/rk3368-cru.h> |
| 19 | |
| 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
| 22 | struct pll_div { |
| 23 | u32 nr; |
| 24 | u32 nf; |
| 25 | u32 no; |
| 26 | }; |
| 27 | |
| 28 | #define OSC_HZ (24 * 1000 * 1000) |
| 29 | #define APLL_L_HZ (800 * 1000 * 1000) |
| 30 | #define APLL_B_HZ (816 * 1000 * 1000) |
| 31 | #define GPLL_HZ (576 * 1000 * 1000) |
| 32 | #define CPLL_HZ (400 * 1000 * 1000) |
| 33 | |
| 34 | #define RATE_TO_DIV(input_rate, output_rate) \ |
| 35 | ((input_rate) / (output_rate) - 1); |
| 36 | |
| 37 | #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
| 38 | |
| 39 | #define PLL_DIVISORS(hz, _nr, _no) { \ |
| 40 | .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \ |
| 41 | _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ |
| 42 | (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ |
| 43 | "divisors on line " __stringify(__LINE__)); |
| 44 | |
| 45 | static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); |
| 46 | static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); |
| 47 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); |
| 48 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); |
| 49 | |
| 50 | /* Get pll rate by id */ |
| 51 | static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, |
| 52 | enum rk3368_pll_id pll_id) |
| 53 | { |
| 54 | uint32_t nr, no, nf; |
| 55 | uint32_t con; |
| 56 | struct rk3368_pll *pll = &cru->pll[pll_id]; |
| 57 | |
| 58 | con = readl(&pll->con3); |
| 59 | |
| 60 | switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { |
| 61 | case PLL_MODE_SLOW: |
| 62 | return OSC_HZ; |
| 63 | case PLL_MODE_NORMAL: |
| 64 | con = readl(&pll->con0); |
| 65 | no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; |
| 66 | nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; |
| 67 | con = readl(&pll->con1); |
| 68 | nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; |
| 69 | |
| 70 | return (24 * nf / (nr * no)) * 1000000; |
| 71 | case PLL_MODE_DEEP_SLOW: |
| 72 | default: |
| 73 | return 32768; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, |
Philipp Tomsich | ddfe77d | 2017-06-22 23:47:11 +0200 | [diff] [blame^] | 78 | const struct pll_div *div) |
Andy Yan | d1dcf85 | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 79 | { |
| 80 | struct rk3368_pll *pll = &cru->pll[pll_id]; |
| 81 | /* All PLLs have same VCO and output frequency range restrictions*/ |
| 82 | uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; |
| 83 | uint output_hz = vco_hz / div->no; |
| 84 | |
| 85 | debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
| 86 | pll, div->nf, div->nr, div->no, vco_hz, output_hz); |
| 87 | |
| 88 | /* enter slow mode and reset pll */ |
| 89 | rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, |
| 90 | PLL_RESET << PLL_RESET_SHIFT); |
| 91 | |
| 92 | rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, |
| 93 | ((div->nr - 1) << PLL_NR_SHIFT) | |
| 94 | ((div->no - 1) << PLL_OD_SHIFT)); |
| 95 | writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); |
Philipp Tomsich | ddfe77d | 2017-06-22 23:47:11 +0200 | [diff] [blame^] | 96 | /* |
| 97 | * BWADJ should be set to NF / 2 to ensure the nominal bandwidth. |
| 98 | * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment". |
| 99 | */ |
| 100 | clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); |
| 101 | |
Andy Yan | d1dcf85 | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 102 | udelay(10); |
| 103 | |
| 104 | /* return from reset */ |
| 105 | rk_clrreg(&pll->con3, PLL_RESET_MASK); |
| 106 | |
| 107 | /* waiting for pll lock */ |
| 108 | while (!(readl(&pll->con1) & PLL_LOCK_STA)) |
| 109 | udelay(1); |
| 110 | |
| 111 | rk_clrsetreg(&pll->con3, PLL_MODE_MASK, |
| 112 | PLL_MODE_NORMAL << PLL_MODE_SHIFT); |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | static void rkclk_init(struct rk3368_cru *cru) |
| 118 | { |
| 119 | u32 apllb, aplll, dpll, cpll, gpll; |
| 120 | |
Philipp Tomsich | ddfe77d | 2017-06-22 23:47:11 +0200 | [diff] [blame^] | 121 | rkclk_set_pll(cru, APLLB, &apll_b_init_cfg); |
| 122 | rkclk_set_pll(cru, APLLL, &apll_l_init_cfg); |
| 123 | rkclk_set_pll(cru, GPLL, &gpll_init_cfg); |
| 124 | rkclk_set_pll(cru, CPLL, &cpll_init_cfg); |
Andy Yan | d1dcf85 | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 125 | |
| 126 | apllb = rkclk_pll_get_rate(cru, APLLB); |
| 127 | aplll = rkclk_pll_get_rate(cru, APLLL); |
| 128 | dpll = rkclk_pll_get_rate(cru, DPLL); |
| 129 | cpll = rkclk_pll_get_rate(cru, CPLL); |
| 130 | gpll = rkclk_pll_get_rate(cru, GPLL); |
| 131 | |
| 132 | debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", |
| 133 | __func__, apllb, aplll, dpll, cpll, gpll); |
| 134 | } |
| 135 | |
| 136 | static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) |
| 137 | { |
| 138 | u32 div, con, con_id, rate; |
| 139 | u32 pll_rate; |
| 140 | |
| 141 | switch (clk_id) { |
| 142 | case SCLK_SDMMC: |
| 143 | con_id = 50; |
| 144 | break; |
| 145 | case SCLK_EMMC: |
| 146 | con_id = 51; |
| 147 | break; |
| 148 | case SCLK_SDIO0: |
| 149 | con_id = 48; |
| 150 | break; |
| 151 | default: |
| 152 | return -EINVAL; |
| 153 | } |
| 154 | |
| 155 | con = readl(&cru->clksel_con[con_id]); |
| 156 | switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) { |
| 157 | case MMC_PLL_SEL_GPLL: |
| 158 | pll_rate = rkclk_pll_get_rate(cru, GPLL); |
| 159 | break; |
| 160 | case MMC_PLL_SEL_24M: |
| 161 | pll_rate = OSC_HZ; |
| 162 | break; |
| 163 | case MMC_PLL_SEL_CPLL: |
| 164 | case MMC_PLL_SEL_USBPHY_480M: |
| 165 | default: |
| 166 | return -EINVAL; |
| 167 | } |
| 168 | div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT; |
| 169 | rate = DIV_TO_RATE(pll_rate, div); |
| 170 | |
| 171 | return rate >> 1; |
| 172 | } |
| 173 | |
| 174 | static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru, |
| 175 | ulong clk_id, ulong rate) |
| 176 | { |
| 177 | u32 div; |
| 178 | u32 con_id; |
| 179 | u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL); |
| 180 | |
| 181 | div = RATE_TO_DIV(gpll_rate, rate << 1); |
| 182 | |
| 183 | switch (clk_id) { |
| 184 | case SCLK_SDMMC: |
| 185 | con_id = 50; |
| 186 | break; |
| 187 | case SCLK_EMMC: |
| 188 | con_id = 51; |
| 189 | break; |
| 190 | case SCLK_SDIO0: |
| 191 | con_id = 48; |
| 192 | break; |
| 193 | default: |
| 194 | return -EINVAL; |
| 195 | } |
| 196 | |
| 197 | if (div > 0x3f) { |
| 198 | div = RATE_TO_DIV(OSC_HZ, rate); |
| 199 | rk_clrsetreg(&cru->clksel_con[con_id], |
| 200 | MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, |
| 201 | (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) | |
| 202 | (div << MMC_CLK_DIV_SHIFT)); |
| 203 | } else { |
| 204 | rk_clrsetreg(&cru->clksel_con[con_id], |
| 205 | MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, |
| 206 | (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) | |
| 207 | div << MMC_CLK_DIV_SHIFT); |
| 208 | } |
| 209 | |
| 210 | return rk3368_mmc_get_clk(cru, clk_id); |
| 211 | } |
| 212 | |
| 213 | static ulong rk3368_clk_get_rate(struct clk *clk) |
| 214 | { |
| 215 | struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); |
| 216 | ulong rate = 0; |
| 217 | |
| 218 | debug("%s id:%ld\n", __func__, clk->id); |
| 219 | switch (clk->id) { |
| 220 | case HCLK_SDMMC: |
| 221 | case HCLK_EMMC: |
| 222 | rate = rk3368_mmc_get_clk(priv->cru, clk->id); |
| 223 | break; |
| 224 | default: |
| 225 | return -ENOENT; |
| 226 | } |
| 227 | |
| 228 | return rate; |
| 229 | } |
| 230 | |
| 231 | static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) |
| 232 | { |
| 233 | struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); |
| 234 | ulong ret = 0; |
| 235 | |
| 236 | debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate); |
| 237 | switch (clk->id) { |
| 238 | case SCLK_SDMMC: |
| 239 | case SCLK_EMMC: |
| 240 | ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate); |
| 241 | break; |
| 242 | default: |
| 243 | return -ENOENT; |
| 244 | } |
| 245 | |
| 246 | return ret; |
| 247 | } |
| 248 | |
| 249 | static struct clk_ops rk3368_clk_ops = { |
| 250 | .get_rate = rk3368_clk_get_rate, |
| 251 | .set_rate = rk3368_clk_set_rate, |
| 252 | }; |
| 253 | |
| 254 | static int rk3368_clk_probe(struct udevice *dev) |
| 255 | { |
| 256 | struct rk3368_clk_priv *priv = dev_get_priv(dev); |
| 257 | |
| 258 | rkclk_init(priv->cru); |
| 259 | |
| 260 | return 0; |
| 261 | } |
| 262 | |
| 263 | static int rk3368_clk_ofdata_to_platdata(struct udevice *dev) |
| 264 | { |
| 265 | struct rk3368_clk_priv *priv = dev_get_priv(dev); |
| 266 | |
| 267 | priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev); |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static int rk3368_clk_bind(struct udevice *dev) |
| 273 | { |
| 274 | int ret; |
| 275 | |
| 276 | /* The reset driver does not have a device node, so bind it here */ |
| 277 | ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev); |
| 278 | if (ret) |
| 279 | error("bind RK3368 reset driver failed: ret=%d\n", ret); |
| 280 | |
| 281 | return ret; |
| 282 | } |
| 283 | |
| 284 | static const struct udevice_id rk3368_clk_ids[] = { |
| 285 | { .compatible = "rockchip,rk3368-cru" }, |
| 286 | { } |
| 287 | }; |
| 288 | |
| 289 | U_BOOT_DRIVER(rockchip_rk3368_cru) = { |
| 290 | .name = "rockchip_rk3368_cru", |
| 291 | .id = UCLASS_CLK, |
| 292 | .of_match = rk3368_clk_ids, |
Philipp Tomsich | cdc6080 | 2017-07-11 20:59:45 +0200 | [diff] [blame] | 293 | .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv), |
Andy Yan | d1dcf85 | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 294 | .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata, |
| 295 | .ops = &rk3368_clk_ops, |
| 296 | .bind = rk3368_clk_bind, |
| 297 | .probe = rk3368_clk_probe, |
| 298 | }; |