blob: 01fe239f8c4d3311cfd465ff2b275b720f95b3cf [file] [log] [blame]
wdenk931da932005-05-07 19:06:32 +00001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * The test exercises SDRAM accesses in burst mode
24 */
25
26#include <common.h>
27#include <exports.h>
28
29#include <commproc.h>
30#include <asm/mmu.h>
31#include <asm/processor.h>
32
33#include <serial.h>
34#include <watchdog.h>
35
36#include "test_burst.h"
37
38/* 8 MB test region of physical RAM */
39#define TEST_PADDR 0x00800000
40/* The uncached virtual region */
41#define TEST_VADDR_NC 0x00800000
42/* The cached virtual region */
43#define TEST_VADDR_C 0x01000000
44/* When an error is detected, the address where the error has been found,
45 and also the current and the expected data will be written to
46 the following flash address
47*/
48#define TEST_FLASH_ADDR 0x40100000
49
50static void test_prepare (void);
51static int test_burst_start (unsigned long size, unsigned long pattern);
52static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
53static int test_mmu_is_on(void);
54static void test_desc(unsigned long size);
55static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
56static void signal_start(void);
57static void signal_error(void);
58static void test_usage(void);
59
60static unsigned long test_pattern [] = {
61 0x00000000,
62 0xffffffff,
63 0x55555555,
64 0xaaaaaaaa,
65};
66
67
68int test_burst (int argc, char *argv[])
69{
70 unsigned long size = CACHE_LINE_SIZE;
71 int res;
72 int i;
73
74 if (argc == 2) {
75 char * d;
76 for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
77 size *= 10;
78 size += *d - '0';
79 }
80 if (size == 0 || *d) {
81 test_usage();
82 return 1;
83 }
84 } else if (argc > 2) {
85 test_usage();
86 return 1;
87 }
88
89 size += (CACHE_LINE_SIZE - 1);
90 size &= ~(CACHE_LINE_SIZE - 1);
91
92 if (!test_mmu_is_on()) {
93 test_prepare();
94 }
95
96 test_desc(size);
97
98 for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); i++) {
99 res = test_burst_start(size, test_pattern[i]);
100 if (res != 0) {
101 goto Done;
102 }
103 }
104Done:
105 return res;
106}
107
108static void test_prepare (void)
109{
110 volatile immap_t *immr = (immap_t *) CFG_IMMR;
111
112 printf ("\n");
113
114 caches_init();
115 disable_interrupts();
116 mmu_init();
117
118 printf ("Interrupts are disabled\n");
119 printf ("I-Cache is ON\n");
120 printf ("D-Cache is ON\n");
121 printf ("MMU is ON\n");
122
123 printf ("\n");
124
125 test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
126 test_map_8M (TEST_PADDR, TEST_VADDR_C, 1);
127
128 test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
129
130 /* Configure PD.8 and PD.9 as general purpose output */
131 immr->im_ioport.iop_pdpar &= ~0x00C0;
132 immr->im_ioport.iop_pddir |= 0x00C0;
133}
134
135static int test_burst_start (unsigned long size, unsigned long pattern)
136{
137 volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
138 volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
139 int i, n;
140 int res = 1;
141
142 printf ("Test pattern %08x ...", pattern);
143
144 n = size / 4;
145
146 for (i = 0; i < n; i ++) {
147 vaddr_c [i] = pattern;
148 }
149 signal_start();
150 flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
151
152 for (i = 0; i < n; i ++) {
153 register unsigned long tmp = vaddr_nc [i];
154 if (tmp != pattern) {
155 test_error("2a", vaddr_nc + i, tmp, pattern);
156 goto Done;
157 }
158 }
159
160 for (i = 0; i < n; i ++) {
161 register unsigned long tmp = vaddr_c [i];
162 if (tmp != pattern) {
163 test_error("2b", vaddr_c + i, tmp, pattern);
164 goto Done;
165 }
166 }
167
168 for (i = 0; i < n; i ++) {
169 vaddr_nc [i] = pattern;
170 }
171
172 for (i = 0; i < n; i ++) {
173 register unsigned long tmp = vaddr_nc [i];
174 if (tmp != pattern) {
175 test_error("3a", vaddr_nc + i, tmp, pattern);
176 goto Done;
177 }
178 }
179
180 signal_start();
181 for (i = 0; i < n; i ++) {
182 register unsigned long tmp = vaddr_c [i];
183 if (tmp != pattern) {
184 test_error("3b", vaddr_c + i, tmp, pattern);
185 goto Done;
186 }
187 }
188
189 res = 0;
190Done:
191 printf(" %s\n", res == 0 ? "OK" : "");
192
193 return res;
194}
195
196static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
197{
198 mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
199 mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
200 mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
201 mtspr (MD_AP, MI_Kp);
202}
203
204static int test_mmu_is_on(void)
205{
206 unsigned long msr;
207
208 asm volatile("mfmsr %0" : "=r" (msr) :);
209
210 return msr & MSR_DR;
211}
212
213static void test_desc(unsigned long size)
214{
215 printf(
216 "The following tests will be conducted:\n"
217 "1) Map %d-byte region of physical RAM at 0x%08x\n"
218 " into two virtual regions:\n"
219 " one cached at 0x%08x and\n"
220 " the the other uncached at 0x%08x.\n",
221 size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
222
223 puts(
224 "2) Fill the cached region with a pattern, and flush the cache\n"
225 "2a) Check the uncached region to match the pattern\n"
226 "2b) Check the cached region to match the pattern\n"
227 "3) Fill the uncached region with a pattern\n"
228 "3a) Check the cached region to match the pattern\n"
229 "3b) Check the uncached region to match the pattern\n"
230 "2b) Change the patterns and go to step 2\n"
231 "\n"
232 );
233}
234
235static void test_error(
236 char * step, volatile void * addr, unsigned long val, unsigned long pattern)
237{
238 volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
239
240 signal_error();
241
242 p[0] = (unsigned long)addr;
243 p[1] = val;
244 p[2] = pattern;
245
246 printf ("\nError at step %s, addr %08x: read %08x, pattern %08x",
247 step, addr, val, pattern);
248}
249
250static void signal_start(void)
251{
252 volatile immap_t *immr = (immap_t *) CFG_IMMR;
253
254 if (immr->im_ioport.iop_pddat & 0x0080) {
255 immr->im_ioport.iop_pddat &= ~0x0080;
256 } else {
257 immr->im_ioport.iop_pddat |= 0x0080;
258 }
259}
260
261static void signal_error(void)
262{
263 volatile immap_t *immr = (immap_t *) CFG_IMMR;
264
265 if (immr->im_ioport.iop_pddat & 0x0040) {
266 immr->im_ioport.iop_pddat &= ~0x0040;
267 } else {
268 immr->im_ioport.iop_pddat |= 0x0040;
269 }
270}
271
272static void test_usage(void)
273{
274 printf("Usage: go 0x40004 [size]\n");
275}