| Pragnesh Patel | 7c45fc9 | 2020-05-29 11:33:34 +0530 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| 2 | # |
| 3 | # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> |
| 4 | |
| 5 | config SIFIVE_FU540 |
| 6 | bool |
| 7 | select ARCH_EARLY_INIT_R |
| Bin Meng | ff8e88a | 2020-08-02 23:09:04 -0700 | [diff] [blame] | 8 | select SUPPORT_SPL |
| 9 | select RAM |
| 10 | select SPL_RAM if SPL |
| Pragnesh Patel | 7c45fc9 | 2020-05-29 11:33:34 +0530 | [diff] [blame] | 11 | imply CPU |
| 12 | imply CPU_RISCV |
| Sean Anderson | c33efaf | 2020-09-28 10:52:21 -0400 | [diff] [blame^] | 13 | imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) |
| Pragnesh Patel | 7c45fc9 | 2020-05-29 11:33:34 +0530 | [diff] [blame] | 14 | imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) |
| 15 | imply CMD_CPU |
| 16 | imply SPL_CPU_SUPPORT |
| 17 | imply SPL_OPENSBI |
| 18 | imply SPL_LOAD_FIT |
| Bin Meng | ff8e88a | 2020-08-02 23:09:04 -0700 | [diff] [blame] | 19 | imply SMP |
| 20 | imply CLK_SIFIVE |
| 21 | imply CLK_SIFIVE_FU540_PRCI |
| 22 | imply SIFIVE_SERIAL |
| 23 | imply MACB |
| 24 | imply MII |
| 25 | imply SPI |
| 26 | imply SPI_SIFIVE |
| 27 | imply MMC |
| 28 | imply MMC_SPI |
| 29 | imply MMC_BROKEN_CD |
| 30 | imply CMD_MMC |
| 31 | imply DM_GPIO |
| 32 | imply SIFIVE_GPIO |
| 33 | imply CMD_GPIO |
| 34 | imply MISC |
| 35 | imply SIFIVE_OTP |
| 36 | imply DM_PWM |
| 37 | imply PWM_SIFIVE |
| Jagan Teki | ff7d25e | 2020-07-15 15:39:00 +0530 | [diff] [blame] | 38 | |
| 39 | if ENV_IS_IN_SPI_FLASH |
| 40 | |
| 41 | config ENV_OFFSET |
| 42 | default 0x505000 |
| 43 | |
| 44 | config ENV_SIZE |
| 45 | default 0x20000 |
| 46 | |
| 47 | config ENV_SECT_SIZE |
| 48 | default 0x10000 |
| 49 | |
| 50 | endif # ENV_IS_IN_SPI_FLASH |