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York Sun7288c2c2015-03-20 19:28:23 -07001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
10#include "ddr.h"
11
12DECLARE_GLOBAL_DATA_PTR;
13
14void fsl_ddr_board_options(memctl_options_t *popts,
15 dimm_params_t *pdimm,
16 unsigned int ctrl_num)
17{
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053018#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun7288c2c2015-03-20 19:28:23 -070019 u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053020#endif
York Sun7288c2c2015-03-20 19:28:23 -070021 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
22 ulong ddr_freq;
23 int slot;
24
25 if (ctrl_num > 2) {
26 printf("Not supported controller number %d\n", ctrl_num);
27 return;
28 }
29
30 for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
31 if (pdimm[slot].n_ranks)
32 break;
33 }
34
35 if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
36 return;
37
38 /*
39 * we use identical timing for all slots. If needed, change the code
40 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
41 */
42 if (popts->registered_dimm_en)
43 pbsp = rdimms[ctrl_num];
44 else
45 pbsp = udimms[ctrl_num];
46
47
48 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
49 * freqency and n_banks specified in board_specific_parameters table.
50 */
51 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
52 while (pbsp->datarate_mhz_high) {
53 if (pbsp->n_ranks == pdimm[slot].n_ranks &&
54 (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
55 if (ddr_freq <= pbsp->datarate_mhz_high) {
56 popts->clk_adjust = pbsp->clk_adjust;
57 popts->wrlvl_start = pbsp->wrlvl_start;
58 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
59 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
60 goto found;
61 }
62 pbsp_highest = pbsp;
63 }
64 pbsp++;
65 }
66
67 if (pbsp_highest) {
68 printf("Error: board specific timing not found for data rate %lu MT/s\n"
69 "Trying to use the highest speed (%u) parameters\n",
70 ddr_freq, pbsp_highest->datarate_mhz_high);
71 popts->clk_adjust = pbsp_highest->clk_adjust;
72 popts->wrlvl_start = pbsp_highest->wrlvl_start;
73 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
74 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
75 } else {
76 panic("DIMM is not supported by this board");
77 }
78found:
79 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
80 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
81 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
82 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
83 pbsp->wrlvl_ctl_3);
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053084#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun7288c2c2015-03-20 19:28:23 -070085 if (ctrl_num == CONFIG_DP_DDR_CTRL) {
86 /* force DDR bus width to 32 bits */
87 popts->data_bus_width = 1;
88 popts->otf_burst_chop_en = 0;
89 popts->burst_length = DDR_BL8;
90 popts->bstopre = 0; /* enable auto precharge */
91 /*
92 * Layout optimization results byte mapping
93 * Byte 0 -> Byte ECC
94 * Byte 1 -> Byte 3
95 * Byte 2 -> Byte 2
96 * Byte 3 -> Byte 1
97 * Byte ECC -> Byte 0
98 */
99 dq_mapping_0 = pdimm[slot].dq_mapping[0];
100 dq_mapping_2 = pdimm[slot].dq_mapping[2];
101 dq_mapping_3 = pdimm[slot].dq_mapping[3];
102 pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
103 pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
104 pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
105 pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
106 pdimm[slot].dq_mapping[6] = dq_mapping_2;
107 pdimm[slot].dq_mapping[7] = dq_mapping_3;
108 pdimm[slot].dq_mapping[8] = dq_mapping_0;
109 pdimm[slot].dq_mapping[9] = 0;
110 pdimm[slot].dq_mapping[10] = 0;
111 pdimm[slot].dq_mapping[11] = 0;
112 pdimm[slot].dq_mapping[12] = 0;
113 pdimm[slot].dq_mapping[13] = 0;
114 pdimm[slot].dq_mapping[14] = 0;
115 pdimm[slot].dq_mapping[15] = 0;
116 pdimm[slot].dq_mapping[16] = 0;
117 pdimm[slot].dq_mapping[17] = 0;
118 }
Prabhakar Kushwaha44937212015-11-09 16:42:07 +0530119#endif
York Sun7288c2c2015-03-20 19:28:23 -0700120 /* To work at higher than 1333MT/s */
121 popts->half_strength_driver_enable = 0;
122 /*
123 * Write leveling override
124 */
125 popts->wrlvl_override = 1;
126 popts->wrlvl_sample = 0x0; /* 32 clocks */
127
128 /*
129 * Rtt and Rtt_WR override
130 */
131 popts->rtt_override = 0;
132
133 /* Enable ZQ calibration */
134 popts->zq_en = 1;
135
136 if (ddr_freq < 2350) {
York Sunc4243ac2015-11-04 10:03:22 -0800137 if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
138 /* four chip-selects */
139 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
140 DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
141 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
142 popts->twot_en = 1; /* enable 2T timing */
143 } else {
144 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
145 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
146 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
147 DDR_CDR2_VREF_RANGE_2;
148 }
York Sun7288c2c2015-03-20 19:28:23 -0700149 } else {
150 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
151 DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
152 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
153 DDR_CDR2_VREF_RANGE_2;
154 }
155}
156
157phys_size_t initdram(int board_type)
158{
159 phys_size_t dram_size;
160
Scott Woodb2d5ac52015-03-24 13:25:02 -0700161#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
162 return fsl_ddr_sdram_size();
163#else
York Sun7288c2c2015-03-20 19:28:23 -0700164 puts("Initializing DDR....using SPD\n");
165
166 dram_size = fsl_ddr_sdram();
Scott Woodb2d5ac52015-03-24 13:25:02 -0700167#endif
York Sun7288c2c2015-03-20 19:28:23 -0700168
169 return dram_size;
170}
171
172void dram_init_banksize(void)
173{
174#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
175 phys_size_t dp_ddr_size;
176#endif
177
178 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
179 if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
180 gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
181 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
182 gd->bd->bi_dram[1].size = gd->ram_size -
183 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
184 } else {
185 gd->bd->bi_dram[0].size = gd->ram_size;
186 }
187
188#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
189 /* initialize DP-DDR here */
190 puts("DP-DDR: ");
191 /*
192 * DDR controller use 0 as the base address for binding.
193 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
194 */
195 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
196 CONFIG_DP_DDR_CTRL,
197 CONFIG_DP_DDR_NUM_CTRLS,
198 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
199 NULL, NULL, NULL);
200 if (dp_ddr_size) {
201 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
202 gd->bd->bi_dram[2].size = dp_ddr_size;
203 } else {
204 puts("Not detected");
205 }
206#endif
207}