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Mingkai Hu4f1d1b72011-07-07 12:29:15 +08001/**
2 * Copyright 2011 Freescale Semiconductor
3 * Author: Mingkai Hu <Mingkai.hu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08006 *
7 * This file provides support for the board-specific CPLD used on some Freescale
8 * reference boards.
9 *
10 * The following macros need to be defined:
11 *
12 * CPLD_BASE - The virtual address of the base of the CPLD register map
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080013 */
14
15#include <common.h>
16#include <command.h>
17#include <asm/io.h>
18
19#include "cpld.h"
20
21static u8 __cpld_read(unsigned int reg)
22{
23 void *p = (void *)CPLD_BASE;
24
25 return in_8(p + reg);
26}
27u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
28
29static void __cpld_write(unsigned int reg, u8 value)
30{
31 void *p = (void *)CPLD_BASE;
32
33 out_8(p + reg, value);
34}
35void cpld_write(unsigned int reg, u8 value)
36 __attribute__((weak, alias("__cpld_write")));
37
38/*
39 * Reset the board. This honors the por_cfg registers.
40 */
41void __cpld_reset(void)
42{
43 CPLD_WRITE(system_rst, 1);
44}
45void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
46
47/**
48 * Set the boot bank to the alternate bank
49 */
50void __cpld_set_altbank(void)
51{
Shaohui Xieba50fee2011-09-13 17:51:39 +080052 u8 reg5 = CPLD_READ(sw_ctl_on);
53
54 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080055 CPLD_WRITE(fbank_sel, 1);
Shaohui Xieba50fee2011-09-13 17:51:39 +080056 CPLD_WRITE(system_rst, 1);
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080057}
58void cpld_set_altbank(void)
59 __attribute__((weak, alias("__cpld_set_altbank")));
60
61/**
62 * Set the boot bank to the default bank
63 */
Shaohui Xieba50fee2011-09-13 17:51:39 +080064void __cpld_set_defbank(void)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080065{
Shaohui Xieba50fee2011-09-13 17:51:39 +080066 CPLD_WRITE(system_rst_default, 1);
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080067}
Shaohui Xieba50fee2011-09-13 17:51:39 +080068void cpld_set_defbank(void)
69 __attribute__((weak, alias("__cpld_set_defbank")));
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080070
71#ifdef DEBUG
72static void cpld_dump_regs(void)
73{
74 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
75 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
76 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
77 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080078 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
79 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
80 printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
81 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
82 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
83 printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
84 printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
85 printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
86 printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
87 putc('\n');
88}
89#endif
90
91int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
92{
93 int rc = 0;
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080094
95 if (argc <= 1)
96 return cmd_usage(cmdtp);
97
98 if (strcmp(argv[1], "reset") == 0) {
99 if (strcmp(argv[2], "altbank") == 0)
100 cpld_set_altbank();
101 else
Shaohui Xieba50fee2011-09-13 17:51:39 +0800102 cpld_set_defbank();
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800103 } else if (strcmp(argv[1], "lane_mux") == 0) {
104 u32 lane = simple_strtoul(argv[2], NULL, 16);
105 u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
106 u8 reg = CPLD_READ(serdes_mux);
107
108 switch (lane) {
109 case 0x6:
110 reg &= ~SERDES_MUX_LANE_6_MASK;
111 reg |= val << SERDES_MUX_LANE_6_SHIFT;
112 break;
113 case 0xa:
114 reg &= ~SERDES_MUX_LANE_A_MASK;
115 reg |= val << SERDES_MUX_LANE_A_SHIFT;
116 break;
117 case 0xc:
118 reg &= ~SERDES_MUX_LANE_C_MASK;
119 reg |= val << SERDES_MUX_LANE_C_SHIFT;
120 break;
121 case 0xd:
122 reg &= ~SERDES_MUX_LANE_D_MASK;
123 reg |= val << SERDES_MUX_LANE_D_SHIFT;
124 break;
125 default:
126 printf("Invalid value\n");
127 break;
128 }
129
130 CPLD_WRITE(serdes_mux, reg);
131#ifdef DEBUG
132 } else if (strcmp(argv[1], "dump") == 0) {
133 cpld_dump_regs();
134#endif
135 } else
136 rc = cmd_usage(cmdtp);
137
138 return rc;
139}
140
141U_BOOT_CMD(
142 cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
143 "Reset the board or pin mulexing selection using the CPLD sequencer",
144 "reset - hard reset to default bank\n"
145 "cpld_cmd reset altbank - reset to alternate bank\n"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800146 "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
Shaohui Xie60820452011-09-22 17:27:29 +0800147 " lane 6: 0 -> slot1\n"
148 " 1 -> SGMII (Default)\n"
149 " lane a: 0 -> slot2\n"
150 " 1 -> AURORA (Default)\n"
151 " lane c: 0 -> slot2\n"
152 " 1 -> SATA0 (Default)\n"
153 " lane d: 0 -> slot2\n"
154 " 1 -> SATA1 (Default)\n"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800155#ifdef DEBUG
156 "cpld_cmd dump - display the CPLD registers\n"
157#endif
158 );